Update safety island with bus_err & atops

This commit is contained in:
Michael Rogenmoser 2023-06-23 16:19:29 +02:00
parent 574000d753
commit 7118c5b963
8 changed files with 98 additions and 11 deletions

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@ -0,0 +1,32 @@
// Generated register defines for bus_err_unit
// Copyright information found in source file:
// Copyright 2022 ETH Zurich and University of Bologna.
// Licensing information found in source file:
//
// SPDX-License-Identifier: SHL-0.51
#ifndef _BUS_ERR_UNIT_REG_DEFS_
#define _BUS_ERR_UNIT_REG_DEFS_
#ifdef __cplusplus
extern "C" {
#endif
// Register width
#define BUS_ERR_UNIT_PARAM_REG_WIDTH 32
// Address of the earliest bus error
#define BUS_ERR_UNIT_ERR_ADDR_REG_OFFSET 0x0
// Top of the address of the earliest bus error
#define BUS_ERR_UNIT_ERR_ADDR_TOP_REG_OFFSET 0x4
// Error code of the last bus error
#define BUS_ERR_UNIT_ERR_CODE_REG_OFFSET 0x8
#ifdef __cplusplus
} // extern "C"
#endif
#endif // _BUS_ERR_UNIT_REG_DEFS_
// End generated register defines for bus_err_unit

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@ -57,17 +57,25 @@
#define ARCHI_CLIC_OFFSET 0x00010000
#define ARCHI_HMR_OFFSET 0x00005000
#define ARCHI_STDOUT_OFFSET 0x00006000
#define ARCHI_FC_TIMER_OFFSET 0x00008000
#define ARCHI_INSTR_ERR_OFFSET 0x00020000
#define ARCHI_DATA_ERR_OFFSET 0x00020010
#define ARCHI_SHADOW_ERR_OFFSET 0x00020020
#define ARCHI_SOC_CTRL_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_SOC_CTRL_OFFSET )
#define ARCHI_BOOT_ROM_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_BOOT_ROM_OFFSET )
#define ARCHI_GLOBAL_PREPEND_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_GLOBAL_PREPEND_OFFSET )
#define ARCHI_DEBUG_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_DEBUG_OFFSET )
#define ARCHI_CLIC_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_CLIC_OFFSET )
#define ARCHI_HMR_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
#define ARCHI_STDOUT_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
#define ARCHI_FC_TIMER_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
#define ARCHI_CLIC_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_CLIC_OFFSET )
#define ARCHI_INSTR_ERR_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_INSTR_ERR_OFFSET )
#define ARCHI_DATA_ERR_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_DATA_ERR_OFFSET )
#define ARCHI_SHADOW_ERR_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_SHADOW_ERR_OFFSET )
#define ARCHI_FC_TIMER_SIZE 0x00000800
#define ARCHI_FC_TIMER_OFFSET 0x0000B000
#define ARCHI_FC_TIMER_ADDR ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
#endif

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@ -34,11 +34,11 @@
#define ARCHI_HAS_L2_MULTI 1
// #define ARCHI_HAS_L1 1
#define ARCHI_LOCAL_PRIV0_ADDR ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
#define ARCHI_LOCAL_PRIV0_SIZE 0x00010000
// #define ARCHI_LOCAL_PRIV0_ADDR ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
// #define ARCHI_LOCAL_PRIV0_SIZE 0x00010000
#define ARCHI_LOCAL_PRIV1_ADDR ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
#define ARCHI_LOCAL_PRIV1_SIZE 0x00010000
// #define ARCHI_LOCAL_PRIV1_ADDR ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
// #define ARCHI_LOCAL_PRIV1_SIZE 0x00010000
// L2 alias
#define ARCHI_L2_PRIV0_ADDR ARCHI_LOCAL_PRIV0_ADDR

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@ -27,5 +27,6 @@
#include "archi/chips/safety-island/memory_map.h"
#include "archi/stdout/stdout_v3.h"
#include "archi/bus_err_unit/bus_err_unit_v1.h"
#endif

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@ -0,0 +1,35 @@
/*
* Copyright (C) 2023 ETH Zurich, University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_BUS_ERR_UNIT_V1_H__
#define __HAL_BUS_ERR_UNIT_V1_H__
#include "archi/pulp.h"
static inline unsigned int data_bus_err_get_addr_32() {
return pulp_read32(ARCHI_DATA_ERR_ADDR+BUS_ERR_UNIT_ERR_ADDR_REG_OFFSET);
}
static inline uint64_t data_bus_err_get_addr_64() {
uint64_t tmp = pulp_read32(ARCHI_DATA_ERR_ADDR+BUS_ERR_UNIT_ERR_ADDR_TOP_REG_OFFSET);
return (tmp << 32) | (uint64_t)(pulp_read32(ARCHI_DATA_ERR_ADDR+BUS_ERR_UNIT_ERR_ADDR_REG_OFFSET));
}
static inline unsigned int data_bus_err_get_err_and_pop() {
return pulp_read32(ARCHI_DATA_ERR_ADDR+BUS_ERR_UNIT_ERR_CODE_REG_OFFSET);
}
#endif // __HAL_BUS_ERR_UNIT_V1_H__

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@ -22,6 +22,7 @@
#include "hal/apb_soc/safety_soc_ctrl.h"
#include "hal/timer/timer_v2.h"
#include "hal/bus_err_unit/bus_err_unit_v1.h"
//#include "hal/cluster_ctrl/cluster_ctrl_v2.h" // TODO Add me!
#endif

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@ -103,8 +103,6 @@ void pi_l1_free(int cid, void *chunk, int size)
#endif
void *pi_l2_malloc(int size)
{
return pos_alloc(&pos_alloc_l2[0], size);
@ -115,6 +113,18 @@ void pi_l2_free(void *_chunk, int size)
return pos_free(&pos_alloc_l2[0], _chunk, size);
}
#if defined(ARCHI_HAS_L2_MULTI)
void *pi_l2_shared_malloc(int size)
{
return pos_alloc(&pos_alloc_l2[2], size);
}
void pi_l2_shared_free(void *_chunk, int size)
{
return pos_free(&pos_alloc_l2[2], _chunk, size);
}
#endif
#if defined(ARCHI_HAS_FC_TCDM)
void *pi_fc_tcdm_malloc(int size)
{

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@ -2,8 +2,8 @@
PULP_LDFLAGS +=
PULP_CFLAGS += -D__cv32e40p__ -U__riscv__ -UARCHI_CORE_HAS_PULPV2
PULP_ARCH_CFLAGS ?= -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
PULP_ARCH_LDFLAGS ?= -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
PULP_ARCH_CFLAGS ?= -march=rv32imac_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
PULP_ARCH_LDFLAGS ?= -march=rv32imac_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
PULP_ARCH_OBJDFLAGS ?=
PULP_CFLAGS += -fdata-sections -ffunction-sections -include chips/safety-island/config.h -I$(PULPRT_HOME)/include/chips/safety-island