Initial safety island modifications

configs/safety_island.sh

@@ -0,0 +1,19 @@
+#!/bin/bash -e
+
+export PULPRT_TARGET=safety_island
+export PULPRUN_TARGET=safety_island
+
+if [  -n "${ZSH_VERSION:-}" ]; then
+        DIR="$(readlink -f -- "${(%):-%x}")"
+        scriptDir="$(dirname $DIR)"
+else
+
+    scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
+
+fi
+
+source $scriptDir/common.sh
+
+export PULPRT_CONFIG_CFLAGS='-DARCHI_ASIC_PER_FREQUENCY=100000000 \
+       -DARCHI_ASIC_FC_FREQUENCY=100000000 \
+       -DARCHI_ASIC_CL_FREQUENCY=100000000'

include/archi/chips/safety-island/memory_map.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_SAFETY_ISLAND_MEMORY_MAP_H__
+#define __ARCHI_CHIPS_SAFETY_ISLAND_MEMORY_MAP_H__
+
+#define ARCHI_SAFETY_ISLAND_BASE_ADDR 0x00000000
+#define ARCHI_SAFETY_ISLAND_PERIPH_OFFSET 0x00200000
+#define ARCHI_SAFETY_ISLAND_MEM_OFFSET 0x00000000
+
+/*
+ * MEMORIES
+ */
+
+#define ARCHI_LOCAL_PRIV0_ADDR  ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
+#define ARCHI_LOCAL_PRIV0_SIZE  0x00010000
+
+#define ARCHI_LOCAL_PRIV1_ADDR  ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
+#define ARCHI_LOCAL_PRIV1_SIZE  0x00010000
+
+// L2 alias
+#define ARCHI_L2_PRIV0_ADDR  ARCHI_LOCAL_PRIV0_ADDR
+#define ARCHI_L2_PRIV0_SIZE  ARCHI_LOCAL_PRIV0_SIZE
+
+#define ARCHI_L2_PRIV1_ADDR  ARCHI_LOCAL_PRIV1_ADDR
+#define ARCHI_L2_PRIV1_SIZE  ARCHI_LOCAL_PRIV1_SIZE
+
+// Shared L2
+#define ARCHI_L2_SHARED_ADDR 0
+#define ARCHI_L2_SHARED_SIZE 0
+
+/*
+ * PERIPHERALS
+ */
+
+#define ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR    ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_PERIPH_OFFSET )
+
+#define ARCHI_SOC_CTRL_OFFSET       0x00000000
+#define ARCHI_BOOT_ROM_OFFSET       0x00001000
+#define ARCHI_GLOBAL_PREPEND_OFFSET 0x00002000
+#define ARCHI_DEBUG_OFFSET          0x00003000
+#define ARCHI_CLIC_OFFSET           0x00010000
+#define ARCHI_HMR_OFFSET            0x00005000
+#define ARCHI_STDOUT_OFFSET     0x00006000
+
+#define ARCHI_SOC_CTRL_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_SOC_CTRL_OFFSET )
+#define ARCHI_BOOT_ROM_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_BOOT_ROM_OFFSET )
+#define ARCHI_GLOBAL_PREPEND_ADDR   ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_GLOBAL_PREPEND_OFFSET )
+#define ARCHI_DEBUG_ADDR            ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_DEBUG_OFFSET )
+#define ARCHI_CLIC_ADDR             ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_CLIC_OFFSET )
+#define ARCHI_HMR_ADDR              ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
+#define ARCHI_STDOUT_ADDR           ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
+
+#endif

include/archi/chips/safety-island/properties.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_SAFETY_ISLAND_PROPERTIES_H__
+#define __ARCHI_CHIPS_SAFETY_ISLAND_PROPERTIES_H__
+
+/*
+ * FPGA
+ */
+
+
+/*
+ * MEMORIES
+ */
+#define ARCHI_SAFETY_ISLAND_BASE_ADDR 0x00000000
+#define ARCHI_SAFETY_ISLAND_PERIPH_OFFSET 0x00200000
+#define ARCHI_SAFETY_ISLAND_MEM_OFFSET 0x00000000
+
+#define ARCHI_HAS_L2                   1
+#define ARCHI_HAS_L2_MULTI             1
+// #define ARCHI_HAS_L1                   1
+
+#define ARCHI_LOCAL_PRIV0_ADDR  ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
+#define ARCHI_LOCAL_PRIV0_SIZE  0x00010000
+
+#define ARCHI_LOCAL_PRIV1_ADDR  ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
+#define ARCHI_LOCAL_PRIV1_SIZE  0x00010000
+
+// L2 alias
+#define ARCHI_L2_PRIV0_ADDR  ARCHI_LOCAL_PRIV0_ADDR
+#define ARCHI_L2_PRIV0_SIZE  ARCHI_LOCAL_PRIV0_SIZE
+
+#define ARCHI_L2_PRIV1_ADDR  ARCHI_LOCAL_PRIV1_ADDR
+#define ARCHI_L2_PRIV1_SIZE  ARCHI_LOCAL_PRIV1_SIZE
+
+// Shared L2
+#define ARCHI_L2_SHARED_ADDR 0
+#define ARCHI_L2_SHARED_SIZE 0
+
+/*
+ * MEMORY ALIAS
+ */
+
+#define ARCHI_HAS_L1_ALIAS             0
+#define ARCHI_HAS_L2_ALIAS             0
+
+/*
+ * IP VERSIONS
+ */
+#define RISCV_VERSION       5
+
+/*
+ * FC
+ */
+
+#define ARCHI_FC_CID         0
+#define ARCHI_HAS_FC_ITC     1
+#define ARCHI_HAS_FC         1
+#define ARCHI_CORE_HAS_1_10  1
+
+
+#endif

include/archi/chips/safety-island/pulp.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_SAFETY_ISLAND_H__
+#define __ARCHI_CHIPS_SAFETY_ISLAND_H__
+
+#include "archi/chips/safety-island/properties.h"
+#include "archi/chips/safety-island/safety_soc_ctrl.h"
+
+// cv32e40p-specific
+#include "archi/cv32e40p/cv32e40p.h"
+#include "archi/riscv/priv_1_12.h"
+
+#include "archi/chips/safety-island/memory_map.h"
+#include "archi/stdout/stdout_v3.h"
+
+#endif

include/archi/chips/safety-island/safety_soc_ctrl.h

@@ -0,0 +1,33 @@
+// Generated register defines for safety_soc_ctrl
+
+// Copyright information found in source file:
+// Copyright 2023 ETH Zurich and University of Bologna
+
+// Licensing information found in source file:
+// 
+// SPDX-License-Identifier: SHL-0.51
+
+#ifndef _SAFETY_SOC_CTRL_REG_DEFS_
+#define _SAFETY_SOC_CTRL_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define SAFETY_SOC_CTRL_PARAM_REG_WIDTH 32
+
+// Core Boot Address
+#define SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET 0x0
+
+// Core Fetch Enable
+#define SAFETY_SOC_CTRL_FETCHEN_REG_OFFSET 0x4
+#define SAFETY_SOC_CTRL_FETCHEN_FETCHEN_BIT 0
+
+// Core Return Status (return value, EOC)
+#define SAFETY_SOC_CTRL_CORESTATUS_REG_OFFSET 0x8
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _SAFETY_SOC_CTRL_REG_DEFS_
+// End generated register defines for safety_soc_ctrl

include/chips/safety-island/config.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SAFETY_ISLAND_CONFIG_H__
+#define __SAFETY_ISLAND_CONFIG_H__
+
+#include "archi/pulp_defs.h"
+
+#define PULP_CHIP CHIP_SAFETY_ISLAND
+#define PULP_CHIP_FAMILY CHIP_SAFETY_ISLAND
+#define CONFIG_PULP 1
+#define PULP_CHIP_STR safety-island
+#define PULP_CHIP_FAMILY_STR safety-island
+
+#endif

include/chips/safety-island/soc.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SAFETY_ISLAND_SOC_H__
+#define __SAFETY_ISLAND_SOC_H__
+
+
+/* TODO we should remove the fll code for control-pulp */
+#define POS_FLL_CL 2
+#define POS_FLL_PERIPH 1
+#define POS_FLL_FC 0
+
+int pos_freq_domains[PI_FREQ_NB_DOMAINS];
+
+
+void pos_soc_init();
+
+static inline int pos_freq_get_fll(int domain)
+{
+    switch (domain)
+    {
+        case PI_FREQ_DOMAIN_FC:
+            return POS_FLL_FC;
+
+        case PI_FREQ_DOMAIN_PERIPH:
+            return POS_FLL_PERIPH;
+
+        case PI_FREQ_DOMAIN_CL:
+        default:
+            return POS_FLL_CL;
+    }
+}
+
+#endif

include/hal/apb_soc/safety_soc_ctrl.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2023 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_SAFETY_SOC_CTRL_H__
+#define __HAL_SAFETY_SOC_CTRL_H__
+
+// Compatability Layer for miniPULP
+
+#include "archi/pulp.h"
+#include "hal/pulp_io.h"
+#define APB_SOC_STATUS_EOC_BIT  31
+
+static inline void apb_soc_bootaddr_set(unsigned int value) {
+  pulp_write32(ARCHI_SOC_CTRL_ADDR + SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET, value);
+}
+
+static inline unsigned int apb_soc_bootaddr_get() {
+  return pulp_read32(ARCHI_SOC_CTRL_ADDR + SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET);
+}
+
+static inline void apb_soc_status_set(unsigned int value) {
+  pulp_write32(ARCHI_SOC_CTRL_ADDR + SAFETY_SOC_CTRL_CORESTATUS_REG_OFFSET, value | (1<<APB_SOC_STATUS_EOC_BIT));
+}
+
+
+
+#endif // __HAL_APB_SOC_MINIPULP_SOC_CTRL_H__

include/hal/chips/safety-island/pulp.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2023 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_CHIPS_SAFETY_ISLAND_H__
+#define __HAL_CHIPS_SAFETY_ISLAND_H__
+
+// cv32e40p-specific
+#include "hal/cv32e40p/cv32e40p.h"
+
+#include "hal/apb_soc/safety_soc_ctrl.h"
+
+#endif

include/implem/alloc.h

@@ -17,6 +17,8 @@
 #ifndef __POS_IMPLEM_ALLOC_H__
 #define __POS_IMPLEM_ALLOC_H__
 
+#include <data/data.h>
+
 void pos_allocs_init();
 
 void pos_alloc_info(pos_alloc_t *a, int *_size, void **first_chunk, int *_nb_chunks);

include/implem/irq.h

@@ -166,7 +166,7 @@ static inline void rt_irq_wait_for_interrupt()
 {
 #if !defined(ARCHI_HAS_FC) || defined(ARCHI_HAS_FC_EU)
     eu_evt_wait();
-#else
+#elif defined(ITC_VERSION)
     hal_itc_wait_for_interrupt();
 #endif
 }

include/pulp.h

@@ -23,11 +23,6 @@
 
 #ifndef LANGUAGE_ASSEMBLY
 
-#include <bench/bench.h>
-#include <archi/pulp.h>
-#include <hal/pulp.h>
-#include <data/data.h>
-
 typedef enum {
   PI_FREQ_DOMAIN_FC     = 0,
   PI_FREQ_DOMAIN_CL     = 1,
@@ -35,6 +30,15 @@ typedef enum {
   PI_FREQ_NB_DOMAINS    = 3
 } pi_freq_domain_e;
 
+#include <stdint.h>
+// #include <bench/bench.h>
+#include <data/data.h>
+#include <implem/implem.h>
+#include <archi/pulp.h>
+#include <hal/pulp.h>
+#include <hal/pulp_io.h>
+
+
 #ifdef ARCHI_HAS_CLUSTER
 
 void cluster_start(int cid, int (*entry)());
@@ -58,7 +62,7 @@ static inline int cluster_wait(int cid)
 
 void _start();
 
-#include <implem/implem.h>
+// #include <implem/implem.h>
 
 #define get_core_id hal_core_id
 #define rt_core_id hal_core_id

kernel/chips/safety-island/link.ld

@@ -0,0 +1,218 @@
+OUTPUT_ARCH(riscv)
+ENTRY( _start )
+MEMORY
+{
+  LOCAL        : ORIGIN = 0x00000004, LENGTH = 0x0001fffc
+  L2           : ORIGIN = 0x10000004, LENGTH = 0x00fffffc
+}
+
+/*
+ * This linker script try to put core data in LOCAL private bank0 and core code
+ * in LOCAL private bank1 to avoid contention between core code and data
+ * as the core has no instruction cache and is so often accessing LOCAL to
+ * get instructions. Everything can be shifted in case one bank is full.
+ *
+ * Cluster code and initialized data are put in L2 to not polute
+ * private banks which are quite small, and also avoid contentions between
+ * cluster cache refill and FC.
+ */
+
+SECTIONS
+{
+  /*
+   * LOCAL PRIVATE BANK0
+   *
+   * Contains FC data
+   */
+
+  .init :
+  {
+    . = ALIGN(4);
+    KEEP( *(.init) )
+  } > LOCAL
+
+
+  .fini :
+  {
+    . = ALIGN(4);
+    KEEP( *(.fini) )
+  } > LOCAL
+
+
+  .preinit_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > LOCAL
+
+
+  .init_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    __CTOR_LIST__ = .;
+    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+    KEEP(*(.ctors.start))
+    KEEP(*(.ctors))
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array ))
+    LONG(0)
+    __CTOR_END__ = .;
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > LOCAL
+
+
+  .fini_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    __DTOR_LIST__ = .;
+    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+    KEEP(*(.dtors.start))
+    KEEP(*(.dtors))
+    LONG(0)
+    __DTOR_END__ = .;
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array ))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > LOCAL
+
+
+  .boot : {
+    . = ALIGN(4);
+    *(.boot)
+    *(.boot.data)
+  } > LOCAL
+
+
+  .rodata : {
+    . = ALIGN(4);
+    *(.rodata);
+    *(.rodata.*)
+    *(.srodata);
+    *(.srodata.*)
+    *(.eh_frame*)
+  } > LOCAL
+
+
+  .got : {
+    . = ALIGN(4);
+    *(.got.plt) * (.igot.plt) *(.got) *(.igot)
+  } > LOCAL
+
+
+  .shbss : {
+    . = ALIGN(4);
+    *(.shbss)
+  } > LOCAL
+
+
+  .talias : {
+  } > LOCAL
+
+
+  .gnu.offload_funcs : {
+    . = ALIGN(4);
+    KEEP(*(.gnu.offload_funcs))
+  } > LOCAL
+
+
+  .gnu.offload_vars : {
+    . = ALIGN(4);
+    KEEP(*(.gnu.offload_vars))
+  } > LOCAL
+
+
+  .stack : {
+    . = ALIGN(4);
+    . = ALIGN(16);
+    stack_start = .;
+    . = . + 0x800;
+    stack = .;
+  } > LOCAL
+
+
+  .data : {
+    . = ALIGN(4);
+    sdata  =  .;
+    _sdata  =  .;
+    *(.data_fc)
+    *(.data_fc.*)
+    *(.data);
+    *(.data.*)
+    *(.sdata);
+    *(.sdata.*)
+    *(.heapl2ram)
+    *(.fcTcdm)
+    *(.fcTcdm.*)
+    *(.fcTcdm_g)
+    *(.fcTcdm_g.*)
+    . = ALIGN(4);
+    edata  =  .;
+    _edata  =  .;
+  } > LOCAL
+
+
+  .bss : {
+    . = ALIGN(8);
+    _bss_start = .;
+    *(.bss)
+    *(.bss.*)
+    *(.sbss)
+    *(.sbss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    _bss_end = .;
+  } > LOCAL
+
+
+  __l2_priv0_end = ALIGN(4);
+
+
+
+
+  /*
+   * LOCAL PRIVATE BANK1
+   *
+   * Contains FC code
+   */
+
+  .vectors MAX(0x00010000,ALIGN(256)) :
+  {
+    __irq_vector_base = .;
+    KEEP(*(.vectors))
+  } > LOCAL
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text)
+    *(.text.*)
+    _etext  =  .;
+    *(.lit)
+    *(.shdata)
+    _endtext = .;
+    . = ALIGN(4);
+  } > LOCAL
+
+  __l2_priv1_end = ALIGN(4);
+
+  /*
+   * L2 SHARED BANKS
+   *
+   * Contains other data such as peripheral data and cluster code and data
+   */
+
+  .l2_data MAX(0x1c010000,ALIGN(4)) :
+  {
+    . = ALIGN(4);
+    *(.l2_data)
+    *(.l2_data.*)
+    *(.data_fc_shared)
+    *(.data_fc_shared.*)
+    . = ALIGN(4);
+  } > L2
+
+  __l2_shared_end = ALIGN(4);
+
+}

kernel/chips/safety-island/soc.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "pulp.h"
+#include "chips/safety-island/soc.h"
+
+void pos_soc_init()
+{
+#if __PLATFORM__ != ARCHI_PLATFORM_FPGA
+  pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_ASIC_FC_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_ASIC_PER_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_ASIC_CL_FREQUENCY;
+#else
+  pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_FPGA_FC_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_FPGA_PER_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_FPGA_CL_FREQUENCY;
+#endif
+}
+

kernel/init.c

@@ -62,7 +62,9 @@ void pos_init_start()
 
   pos_irq_init();
 
+#if defined(EU_VERSION)
   pos_soc_event_init();
+#endif
 
   // Initialize first the memory allocators and the utils so that they are
   // available for constructors, especially to let them declare

rules/pulpos/default_rules.mk

@@ -152,7 +152,7 @@ endif
 #
 # VSIM Flags
 #
-vsim_flags ?= +ENTRY_POINT=0x1c008080 -permit_unmatched_virtual_intf -gBAUDRATE=115200
+vsim_flags ?= +ENTRY_POINT=0x00010080 -permit_unmatched_virtual_intf -gBAUDRATE=115200
 
 ifdef CONFIG_PLUSARG_SIM
 

rules/pulpos/src.mk

@@ -6,7 +6,7 @@ ifeq '$(CONFIG_LIBC_MINIMAL)' '1'
 PULP_SRCS += lib/libc/minimal/io.c lib/libc/minimal/fprintf.c lib/libc/minimal/prf.c lib/libc/minimal/sprintf.c
 endif
 
-PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c kernel/soc_event.c kernel/bench.c drivers/uart.c
+PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c# kernel/soc_event.c kernel/bench.c drivers/uart.c
 
 PULP_ASM_SRCS += kernel/irq_asm.S
 

rules/pulpos/targets/safety_island.mk

@@ -0,0 +1,36 @@
+
+PULP_LDFLAGS +=
+PULP_CFLAGS += -D__cv32e40p__ -U__riscv__ -UARCHI_CORE_HAS_PULPV2
+
+PULP_ARCH_CFLAGS ?=  -march=rv32imcxgap9
+PULP_ARCH_OBJDFLAGS ?= -march=riscv32imcxgap9
+PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imcxgap9
+
+# PULP_ARCH_CFLAGS ?=  -march=rv32imc_zfinx_xcorev -mno-nohwloop
+# PULP_ARCH_LDFLAGS ?=  -march=rv32imc_zfinx_xcorev -mno-nohwloop
+# PULP_ARCH_OBJDFLAGS ?=
+
+PULP_CFLAGS    += -fdata-sections -ffunction-sections -include chips/safety-island/config.h -I$(PULPRT_HOME)/include/chips/safety-island
+PULP_OMP_CFLAGS    += -fopenmp -mnativeomp
+PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/safety-island/link.ld -lgcc
+
+PULP_CC = riscv32-unknown-elf-gcc
+PULP_AR ?= riscv32-unknown-elf-ar
+PULP_LD ?= riscv32-unknown-elf-gcc
+PULP_OBJDUMP ?= riscv32-unknown-elf-objdump
+
+fc/archi=riscv
+pe/archi=riscv
+pulp_chip=safety-island
+pulp_chip_family=safety-island
+
+PULP_SRCS     += kernel/chips/safety-island/soc.c
+
+
+include $(PULPRT_HOME)/rules/pulpos/configs/default.mk
+
+ifeq '$(platform)' 'fpga'
+CONFIG_IO_UART=1
+endif
+
+include $(PULPRT_HOME)/rules/pulpos/default_rules.mk