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Add AVS BUS support and basic test

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* Add configuration register to set AVS mode
* Add connections to the SPI controller and txrx interface
* Set idle level of sdio[0] signal of SPI master to '1', according to
the AVS protocol
* Add SPI slave device capability to trigger an event for requesting a read from
master by driving low the MISO (SDATA for AVS) when AVS mode is set.
This happens during tx/rx idle phases
* Add basic Write commit/Read test with pulp-runtime. AVS slave is
simulated in tb_avs.sv and tb_avs_fpga.sv.
This commit is contained in:
Corrado Bonfanti 2021-12-13 12:18:56 +01:00 committed by aottaviano
parent 735f29948c
commit 18ab940220
2 changed files with 23 additions and 20 deletions
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40
include/archi/chips/control-pulp/properties.h
View file

@ -112,33 +112,31 @@
#define ARCHI_UDMA_HAS_SPIM 1 #define ARCHI_UDMA_HAS_SPIM 1
#define ARCHI_UDMA_HAS_UART 1 #define ARCHI_UDMA_HAS_UART 1
#define ARCHI_UDMA_HAS_SDIO 1 #define ARCHI_UDMA_HAS_SDIO 0
#define ARCHI_UDMA_HAS_I2C 1 #define ARCHI_UDMA_HAS_I2C 1
#define ARCHI_UDMA_HAS_I2S 1 #define ARCHI_UDMA_HAS_I2S 0
#define ARCHI_UDMA_HAS_CAM 1 #define ARCHI_UDMA_HAS_CAM 0
#define ARCHI_UDMA_HAS_TRACER 1 #define ARCHI_UDMA_HAS_TRACER 0
#define ARCHI_UDMA_HAS_FILTER 1 #define ARCHI_UDMA_HAS_FILTER 0
#define ARCHI_UDMA_NB_SPIM 1 #define ARCHI_UDMA_NB_SPIM 8
#define ARCHI_UDMA_NB_UART 1 #define ARCHI_UDMA_NB_UART 1
#define ARCHI_UDMA_NB_SDIO 1 #define ARCHI_UDMA_NB_SDIO 0
#define ARCHI_UDMA_NB_I2C 1 #define ARCHI_UDMA_NB_I2C 12
#define ARCHI_UDMA_NB_I2S 1 #define ARCHI_UDMA_NB_I2S 0
#define ARCHI_UDMA_NB_CAM 1 #define ARCHI_UDMA_NB_CAM 0
#define ARCHI_UDMA_NB_TRACER 1 #define ARCHI_UDMA_NB_TRACER 0
#define ARCHI_UDMA_NB_FILTER 1 #define ARCHI_UDMA_NB_FILTER 1
#define ARCHI_UDMA_UART_ID(id) 0 #define ARCHI_UDMA_UART_ID(id) 0
#define ARCHI_UDMA_SPIM_ID(id) (1 + (id)) #define ARCHI_UDMA_SPIM_ID(id) (1 + (id))
#define ARCHI_UDMA_I2C_ID(id) (9 + (id)) #define ARCHI_UDMA_I2C_ID(id) (9 + (id))
#define ARCHI_UDMA_SDIO_ID(id) (21 + (id)) #define ARCHI_UDMA_FILTER_ID(id) (21 + (id))
#define ARCHI_UDMA_FILTER_ID(id) (22 + (id))
#define ARCHI_UDMA_TRACER_ID(id) 23
#define ARCHI_UDMA_TGEN_ID(id) 24
#define ARCHI_NB_PERIPH 25
#define ARCHI_NB_PERIPH 22
#define ARCHI_UDMA_NB_I2C_MAX 12
#define ARCHI_UDMA_NB_SPIM_MAX 8
/* /*
* FLLS * FLLS
@ -161,9 +159,12 @@
#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2 #define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT (1<<ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2) #define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT (1<<ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
#define ARCHI_SOC_EVENT_UDMA_FIRST_EVT 0 #define ARCHI_SOC_EVENT_UDMA_FIRST_EVT 0
#define ARCHI_SOC_EVENT_UDMA_NB_EVT (ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT * ARCHI_NB_PERIPH) #define ARCHI_SOC_EVENT_UDMA_NB_EVT (ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT * ARCHI_NB_PERIPH_MAX)
#define ARCHI_SOC_EVENT_UDMA_NB_TGEN_EVT 6 #define ARCHI_SOC_EVENT_UDMA_NB_TGEN_EVT 6
#define ARCHI_SOC_EVENT_UDMA_NB_EVT_MAX 32*4
#define ARCHI_NB_PERIPH_MAX ((ARCHI_SOC_EVENT_UDMA_NB_EVT_MAX-ARCHI_UDMA_NB_SPIM_MAX-ARCHI_UDMA_NB_I2C_MAX)>>2)
#define ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(x) ((x)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT) #define ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(x) ((x)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT)
#define ARCHI_SOC_EVENT_UART0_RX 0 #define ARCHI_SOC_EVENT_UART0_RX 0
@ -175,6 +176,7 @@
#define ARCHI_SOC_EVENT_SPIM_TX (id) (5 + (id) * 4) #define ARCHI_SOC_EVENT_SPIM_TX (id) (5 + (id) * 4)
#define ARCHI_SOC_EVENT_SPIM_CMD(id) (6 + (id) * 4) #define ARCHI_SOC_EVENT_SPIM_CMD(id) (6 + (id) * 4)
#define ARCHI_SOC_EVENT_SPIM_EOT(id) (7 + (id) * 4) #define ARCHI_SOC_EVENT_SPIM_EOT(id) (7 + (id) * 4)
#define ARCHI_SOC_EVENT_SPIM_REQ(id) (ARCHI_SOC_EVENT_UDMA_NB_EVT + (id))
#define ARCHI_SOC_EVENT_I2C0_RX 8 #define ARCHI_SOC_EVENT_I2C0_RX 8
#define ARCHI_SOC_EVENT_I2C0_TX 9 #define ARCHI_SOC_EVENT_I2C0_TX 9

3
include/hal/udma/spim/udma_spim_v3.h
View file

@ -23,6 +23,7 @@
#define UDMA_SPIM_CMD_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x20) #define UDMA_SPIM_CMD_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x20)
#define UDMA_SPIM_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x00) #define UDMA_SPIM_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x00)
#define UDMA_SPIM_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x10) #define UDMA_SPIM_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x10)
#define UDMA_SPIM_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) #define UDMA_SPIM_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET + 0x10)
#define UDMA_SPIM_AVS(id) (UDMA_SPIM_CUSTOM_ADDR(id) + 0x04)
#endif #endif