treewide: Add carfield target

configs/carfield.sh

@@ -0,0 +1,19 @@
+#!/bin/bash -e
+
+export PULPRT_TARGET=carfield
+export PULPRUN_TARGET=carfield
+
+if [  -n "${ZSH_VERSION:-}" ]; then
+        DIR="$(readlink -f -- "${(%):-%x}")"
+        scriptDir="$(dirname $DIR)"
+else
+
+    scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
+
+fi
+
+source $scriptDir/common.sh
+
+export PULPRT_CONFIG_CFLAGS='-DARCHI_ASIC_PER_FREQUENCY=100000000 \
+       -DARCHI_ASIC_FC_FREQUENCY=100000000 \
+       -DARCHI_ASIC_CL_FREQUENCY=100000000'

include/archi/chips/carfield/memory_map.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_CARFIELD_MEMORY_MAP_H__
+#define __ARCHI_CHIPS_CARFIELD_MEMORY_MAP_H__
+
+// Shared L2
+#define ARCHI_L2_SHARED_ADDR 0x78000000
+#define ARCHI_L2_SHARED_SIZE 0x400000
+// TODO: Add other peripherals
+
+#define ARCHI_SAFETY_ISLAND_BASE_ADDR 0x60000000
+#define ARCHI_SAFETY_ISLAND_PERIPH_OFFSET 0x00200000
+#define ARCHI_SAFETY_ISLAND_MEM_OFFSET 0x00000000
+
+/*
+ * MEMORIES
+ */
+
+#define ARCHI_LOCAL_PRIV_BANK_SIZE 0x00010000
+
+#define ARCHI_LOCAL_PRIV0_ADDR  ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
+#define ARCHI_LOCAL_PRIV0_SIZE  ARCHI_LOCAL_PRIV_BANK_SIZE
+
+#define ARCHI_LOCAL_PRIV1_ADDR  ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
+#define ARCHI_LOCAL_PRIV1_SIZE  ARCHI_LOCAL_PRIV_BANK_SIZE
+
+// L2 alias
+#define ARCHI_L2_PRIV0_ADDR  ARCHI_LOCAL_PRIV0_ADDR
+#define ARCHI_L2_PRIV0_SIZE  ARCHI_LOCAL_PRIV0_SIZE
+
+#define ARCHI_L2_PRIV1_ADDR  ARCHI_LOCAL_PRIV1_ADDR
+#define ARCHI_L2_PRIV1_SIZE  ARCHI_LOCAL_PRIV1_SIZE
+
+/*
+ * PERIPHERALS
+ */
+
+#define ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR    ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_PERIPH_OFFSET )
+
+#define ARCHI_SOC_CTRL_OFFSET       0x00000000
+#define ARCHI_BOOT_ROM_OFFSET       0x00001000
+#define ARCHI_GLOBAL_PREPEND_OFFSET 0x00002000
+#define ARCHI_DEBUG_OFFSET          0x00003000
+#define ARCHI_CLIC_OFFSET           0x00010000
+#define ARCHI_HMR_OFFSET            0x00005000
+#define ARCHI_STDOUT_OFFSET         0x00006000
+
+#define ARCHI_SOC_CTRL_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_SOC_CTRL_OFFSET )
+#define ARCHI_BOOT_ROM_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_BOOT_ROM_OFFSET )
+#define ARCHI_GLOBAL_PREPEND_ADDR   ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_GLOBAL_PREPEND_OFFSET )
+#define ARCHI_DEBUG_ADDR            ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_DEBUG_OFFSET )
+#define ARCHI_CLIC_ADDR             ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_CLIC_OFFSET )
+#define ARCHI_HMR_ADDR              ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
+#define ARCHI_STDOUT_ADDR           ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
+
+#define ARCHI_FC_TIMER_SIZE            0x00000800
+#define ARCHI_FC_TIMER_OFFSET          0x0000B000
+#define ARCHI_FC_TIMER_ADDR            ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
+
+#endif

include/archi/chips/carfield/properties.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_CARFIELD_PROPERTIES_H__
+#define __ARCHI_CHIPS_CARFIELD_PROPERTIES_H__
+
+/*
+ * FPGA
+ */
+
+
+/*
+ * MEMORIES
+ */
+#define ARCHI_SAFETY_ISLAND_BASE_ADDR 0x00000000
+#define ARCHI_SAFETY_ISLAND_PERIPH_OFFSET 0x00200000
+#define ARCHI_SAFETY_ISLAND_MEM_OFFSET 0x00000000
+
+#define ARCHI_HAS_L2                   1
+#define ARCHI_HAS_L2_MULTI             1
+// #define ARCHI_HAS_L1                   1
+
+#define ARCHI_LOCAL_PRIV0_ADDR  ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
+#define ARCHI_LOCAL_PRIV0_SIZE  0x00010000
+
+#define ARCHI_LOCAL_PRIV1_ADDR  ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
+#define ARCHI_LOCAL_PRIV1_SIZE  0x00010000
+
+// L2 alias
+#define ARCHI_L2_PRIV0_ADDR  ARCHI_LOCAL_PRIV0_ADDR
+#define ARCHI_L2_PRIV0_SIZE  ARCHI_LOCAL_PRIV0_SIZE
+
+#define ARCHI_L2_PRIV1_ADDR  ARCHI_LOCAL_PRIV1_ADDR
+#define ARCHI_L2_PRIV1_SIZE  ARCHI_LOCAL_PRIV1_SIZE
+
+// Shared L2
+#define ARCHI_L2_SHARED_ADDR 0
+#define ARCHI_L2_SHARED_SIZE 0
+
+/*
+ * MEMORY ALIAS
+ */
+
+#define ARCHI_HAS_L1_ALIAS             0
+#define ARCHI_HAS_L2_ALIAS             0
+
+/*
+ * IP VERSIONS
+ */
+#define RISCV_VERSION       5
+
+/*
+ * FC
+ */
+
+#define ARCHI_FC_CID         0
+#define ARCHI_HAS_FC_ITC     1
+#define ARCHI_HAS_FC         1
+#define ARCHI_CORE_HAS_1_10  1
+
+
+#endif

include/archi/chips/carfield/pulp.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_CARFIELD_H__
+#define __ARCHI_CHIPS_CARFIELD_H__
+
+#include "archi/chips/carfield/properties.h"
+#include "archi/chips/carfield/safety_soc_ctrl.h"
+
+// cv32e40p-specific
+#include "archi/cv32e40p/cv32e40p.h"
+#include "archi/riscv/priv_1_12.h"
+
+#include "archi/chips/carfield/memory_map.h"
+#include "archi/stdout/stdout_v3.h"
+
+#endif

include/archi/chips/carfield/safety_soc_ctrl.h

@@ -0,0 +1,33 @@
+// Generated register defines for safety_soc_ctrl
+
+// Copyright information found in source file:
+// Copyright 2023 ETH Zurich and University of Bologna
+
+// Licensing information found in source file:
+// 
+// SPDX-License-Identifier: SHL-0.51
+
+#ifndef _SAFETY_SOC_CTRL_REG_DEFS_
+#define _SAFETY_SOC_CTRL_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define SAFETY_SOC_CTRL_PARAM_REG_WIDTH 32
+
+// Core Boot Address
+#define SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET 0x0
+
+// Core Fetch Enable
+#define SAFETY_SOC_CTRL_FETCHEN_REG_OFFSET 0x4
+#define SAFETY_SOC_CTRL_FETCHEN_FETCHEN_BIT 0
+
+// Core Return Status (return value, EOC)
+#define SAFETY_SOC_CTRL_CORESTATUS_REG_OFFSET 0x8
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _SAFETY_SOC_CTRL_REG_DEFS_
+// End generated register defines for safety_soc_ctrl

include/archi/chips/safety-island/memory_map.h

@@ -18,6 +18,9 @@
 #ifndef __ARCHI_CHIPS_SAFETY_ISLAND_MEMORY_MAP_H__
 #define __ARCHI_CHIPS_SAFETY_ISLAND_MEMORY_MAP_H__
 
+#define ARCHI_L2_SHARED_ADDR 0x00000000
+#define ARCHI_L2_SHARED_SIZE 0x00000000
+
 #define ARCHI_SAFETY_ISLAND_BASE_ADDR 0x00000000
 #define ARCHI_SAFETY_ISLAND_PERIPH_OFFSET 0x00200000
 #define ARCHI_SAFETY_ISLAND_MEM_OFFSET 0x00000000
@@ -26,11 +29,13 @@
  * MEMORIES
  */
 
+#define ARCHI_LOCAL_PRIV_BANK_SIZE 0x00010000
+
 #define ARCHI_LOCAL_PRIV0_ADDR  ( ARCHI_SAFETY_ISLAND_BASE_ADDR + ARCHI_SAFETY_ISLAND_MEM_OFFSET )
-#define ARCHI_LOCAL_PRIV0_SIZE  0x00010000
+#define ARCHI_LOCAL_PRIV0_SIZE  ARCHI_LOCAL_PRIV_BANK_SIZE
 
 #define ARCHI_LOCAL_PRIV1_ADDR  ( ARCHI_LOCAL_PRIV0_ADDR + ARCHI_LOCAL_PRIV0_SIZE )
-#define ARCHI_LOCAL_PRIV1_SIZE  0x00010000
+#define ARCHI_LOCAL_PRIV1_SIZE  ARCHI_LOCAL_PRIV_BANK_SIZE
 
 // L2 alias
 #define ARCHI_L2_PRIV0_ADDR  ARCHI_LOCAL_PRIV0_ADDR
@@ -39,10 +44,6 @@
 #define ARCHI_L2_PRIV1_ADDR  ARCHI_LOCAL_PRIV1_ADDR
 #define ARCHI_L2_PRIV1_SIZE  ARCHI_LOCAL_PRIV1_SIZE
 
-// Shared L2
-#define ARCHI_L2_SHARED_ADDR 0
-#define ARCHI_L2_SHARED_SIZE 0
-
 /*
  * PERIPHERALS
  */
@@ -55,7 +56,7 @@
 #define ARCHI_DEBUG_OFFSET          0x00003000
 #define ARCHI_CLIC_OFFSET           0x00010000
 #define ARCHI_HMR_OFFSET            0x00005000
-#define ARCHI_STDOUT_OFFSET     0x00006000
+#define ARCHI_STDOUT_OFFSET         0x00006000
 
 #define ARCHI_SOC_CTRL_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_SOC_CTRL_OFFSET )
 #define ARCHI_BOOT_ROM_ADDR         ( ARCHI_SAFETY_ISLAND_PERIPHERALS_ADDR + ARCHI_BOOT_ROM_OFFSET )

include/chips/carfield/config.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CARFIELD_CONFIG_H__
+#define __CARFIELD_CONFIG_H__
+
+#include "archi/pulp_defs.h"
+
+#define PULP_CHIP CHIP_CARFIELD
+#define PULP_CHIP_FAMILY CHIP_CARFIELD
+#define CONFIG_PULP 1
+#define PULP_CHIP_STR carfield
+#define PULP_CHIP_FAMILY_STR carfield
+
+#endif

include/chips/carfield/soc.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SAFETY_ISLAND_SOC_H__
+#define __SAFETY_ISLAND_SOC_H__
+
+
+/* TODO we should remove the fll code for control-pulp */
+#define POS_FLL_CL 2
+#define POS_FLL_PERIPH 1
+#define POS_FLL_FC 0
+
+int pos_freq_domains[PI_FREQ_NB_DOMAINS];
+
+
+void pos_soc_init();
+
+static inline int pos_freq_get_fll(int domain)
+{
+    switch (domain)
+    {
+        case PI_FREQ_DOMAIN_FC:
+            return POS_FLL_FC;
+
+        case PI_FREQ_DOMAIN_PERIPH:
+            return POS_FLL_PERIPH;
+
+        case PI_FREQ_DOMAIN_CL:
+        default:
+            return POS_FLL_CL;
+    }
+}
+
+#endif

include/hal/chips/carfield/pulp.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2023 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_CHIPS_CARFIELD_H__
+#define __HAL_CHIPS_CARFIELD_H__
+
+// cv32e40p-specific
+#include "hal/cv32e40p/cv32e40p.h"
+
+#include "hal/apb_soc/safety_soc_ctrl.h"
+#include "hal/timer/timer_v2.h"
+//#include "hal/cluster_ctrl/cluster_ctrl_v2.h" // TODO Add me!
+
+#endif

kernel/chips/carfield/link.ld

@@ -0,0 +1,218 @@
+OUTPUT_ARCH(riscv)
+ENTRY( _start )
+MEMORY
+{
+  LOCAL        : ORIGIN = 0x60000004, LENGTH = 0x6001fffc
+  L2           : ORIGIN = 0x10000004, LENGTH = 0x00fffffc
+}
+
+/*
+ * This linker script try to put core data in LOCAL private bank0 and core code
+ * in LOCAL private bank1 to avoid contention between core code and data
+ * as the core has no instruction cache and is so often accessing LOCAL to
+ * get instructions. Everything can be shifted in case one bank is full.
+ *
+ * Cluster code and initialized data are put in L2 to not polute
+ * private banks which are quite small, and also avoid contentions between
+ * cluster cache refill and FC.
+ */
+
+SECTIONS
+{
+  /*
+   * LOCAL PRIVATE BANK0
+   *
+   * Contains FC data
+   */
+
+  .init :
+  {
+    . = ALIGN(4);
+    KEEP( *(.init) )
+  } > LOCAL
+
+
+  .fini :
+  {
+    . = ALIGN(4);
+    KEEP( *(.fini) )
+  } > LOCAL
+
+
+  .preinit_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > LOCAL
+
+
+  .init_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    __CTOR_LIST__ = .;
+    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+    KEEP(*(.ctors.start))
+    KEEP(*(.ctors))
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array ))
+    LONG(0)
+    __CTOR_END__ = .;
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > LOCAL
+
+
+  .fini_array : {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    __DTOR_LIST__ = .;
+    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+    KEEP(*(.dtors.start))
+    KEEP(*(.dtors))
+    LONG(0)
+    __DTOR_END__ = .;
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array ))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > LOCAL
+
+
+  .boot : {
+    . = ALIGN(4);
+    *(.boot)
+    *(.boot.data)
+  } > LOCAL
+
+
+  .rodata : {
+    . = ALIGN(4);
+    *(.rodata);
+    *(.rodata.*)
+    *(.srodata);
+    *(.srodata.*)
+    *(.eh_frame*)
+  } > LOCAL
+
+
+  .got : {
+    . = ALIGN(4);
+    *(.got.plt) * (.igot.plt) *(.got) *(.igot)
+  } > LOCAL
+
+
+  .shbss : {
+    . = ALIGN(4);
+    *(.shbss)
+  } > LOCAL
+
+
+  .talias : {
+  } > LOCAL
+
+
+  .gnu.offload_funcs : {
+    . = ALIGN(4);
+    KEEP(*(.gnu.offload_funcs))
+  } > LOCAL
+
+
+  .gnu.offload_vars : {
+    . = ALIGN(4);
+    KEEP(*(.gnu.offload_vars))
+  } > LOCAL
+
+
+  .stack : {
+    . = ALIGN(4);
+    . = ALIGN(16);
+    stack_start = .;
+    . = . + 0x800;
+    stack = .;
+  } > LOCAL
+
+
+  .data : {
+    . = ALIGN(4);
+    sdata  =  .;
+    _sdata  =  .;
+    *(.data_fc)
+    *(.data_fc.*)
+    *(.data);
+    *(.data.*)
+    *(.sdata);
+    *(.sdata.*)
+    *(.heapl2ram)
+    *(.fcTcdm)
+    *(.fcTcdm.*)
+    *(.fcTcdm_g)
+    *(.fcTcdm_g.*)
+    . = ALIGN(4);
+    edata  =  .;
+    _edata  =  .;
+  } > LOCAL
+
+
+  .bss : {
+    . = ALIGN(8);
+    _bss_start = .;
+    *(.bss)
+    *(.bss.*)
+    *(.sbss)
+    *(.sbss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    _bss_end = .;
+  } > LOCAL
+
+
+  __l2_priv0_end = ALIGN(4);
+
+
+
+
+  /*
+   * LOCAL PRIVATE BANK1
+   *
+   * Contains FC code
+   */
+
+  .vectors MAX(0x60010000,ALIGN(256)) :
+  {
+    __irq_vector_base = .;
+    KEEP(*(.vectors))
+  } > LOCAL
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text)
+    *(.text.*)
+    _etext  =  .;
+    *(.lit)
+    *(.shdata)
+    _endtext = .;
+    . = ALIGN(4);
+  } > LOCAL
+
+  __l2_priv1_end = ALIGN(4);
+
+  /*
+   * L2 SHARED BANKS
+   *
+   * Contains other data such as peripheral data and cluster code and data
+   */
+
+  .l2_data MAX(0x1c010000,ALIGN(4)) :
+  {
+    . = ALIGN(4);
+    *(.l2_data)
+    *(.l2_data.*)
+    *(.data_fc_shared)
+    *(.data_fc_shared.*)
+    . = ALIGN(4);
+  } > L2
+
+  __l2_shared_end = ALIGN(4);
+
+}

kernel/chips/carfield/soc.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2023 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "pulp.h"
+#include "chips/safety-island/soc.h"
+
+void pos_soc_init()
+{
+#if __PLATFORM__ != ARCHI_PLATFORM_FPGA
+  pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_ASIC_FC_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_ASIC_PER_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_ASIC_CL_FREQUENCY;
+#else
+  pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_FPGA_FC_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_FPGA_PER_FREQUENCY;
+  pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_FPGA_CL_FREQUENCY;
+#endif
+}
+

rules/pulpos/targets/carfield.mk

@@ -0,0 +1,32 @@
+
+PULP_LDFLAGS +=
+PULP_CFLAGS += -D__cv32e40p__ -U__riscv__ -UARCHI_CORE_HAS_PULPV2
+
+PULP_ARCH_CFLAGS    ?= -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
+PULP_ARCH_LDFLAGS   ?= -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop
+PULP_ARCH_OBJDFLAGS ?=
+
+PULP_CFLAGS    += -fdata-sections -ffunction-sections -include chips/carfield/config.h -I$(PULPRT_HOME)/include/chips/carfield
+PULP_OMP_CFLAGS    += -fopenmp -mnativeomp
+PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/carfield/link.ld -lgcc
+
+PULP_CC = riscv32-unknown-elf-gcc
+PULP_AR ?= riscv32-unknown-elf-ar
+PULP_LD ?= riscv32-unknown-elf-gcc
+PULP_OBJDUMP ?= riscv32-unknown-elf-objdump
+
+fc/archi=riscv
+pe/archi=riscv
+pulp_chip=carfield
+pulp_chip_family=carfield
+
+PULP_SRCS     += kernel/chips/carfield/soc.c
+
+
+include $(PULPRT_HOME)/rules/pulpos/configs/default.mk
+
+ifeq '$(platform)' 'fpga'
+CONFIG_IO_UART=1
+endif
+
+include $(PULPRT_HOME)/rules/pulpos/default_rules.mk