From 0014e6f91093a18adb40fa142f6178b7ce16f704 Mon Sep 17 00:00:00 2001
From: Luca Valente <luca.valente2@unibo.it>
Date: Tue, 18 May 2021 19:48:58 +0200
Subject: [PATCH] cpu_per_start now arbitrarily associates perf counter with
 event

---
 include/hal/cv32e40p/cv32e40p.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/include/hal/cv32e40p/cv32e40p.h b/include/hal/cv32e40p/cv32e40p.h
index 039b92d..59ae522 100644
--- a/include/hal/cv32e40p/cv32e40p.h
+++ b/include/hal/cv32e40p/cv32e40p.h
@@ -296,7 +296,23 @@ static inline void cpu_perf_conf(unsigned int confMask)
  * the rest of the config can be given through conf parameter */
 static inline void cpu_perf_start() {
 #ifndef PLP_NO_PERF_COUNTERS
+  // enable all counters
   asm volatile("csrc 0x320, %0" : : "r"(0xffffffff));
+  // arbitrary association of one event to one counter,
+  // just the implemented ones will increase
+  asm volatile("csrw 0x323, %0" : : "r"(1<<CSR_PCER_LD_STALL));
+  asm volatile("csrw 0x324, %0" : : "r"(1<<CSR_PCER_JMP_STALL));
+  asm volatile("csrw 0x325, %0" : : "r"(1<<CSR_PCER_IMISS));
+  asm volatile("csrw 0x326, %0" : : "r"(1<<CSR_PCER_LD));
+  asm volatile("csrw 0x327, %0" : : "r"(1<<CSR_PCER_ST));
+  asm volatile("csrw 0x328, %0" : : "r"(1<<CSR_PCER_JUMP));
+  asm volatile("csrw 0x329, %0" : : "r"(1<<CSR_PCER_BRANCH));
+  asm volatile("csrw 0x32A, %0" : : "r"(1<<CSR_PCER_TAKEN_BRANCH));
+  asm volatile("csrw 0x32B, %0" : : "r"(1<<CSR_PCER_COMP_INSTR));
+  asm volatile("csrw 0x32C, %0" : : "r"(1<<CSR_PCER_PIPE_STALL));
+  asm volatile("csrw 0x32D, %0" : : "r"(1<<CSR_PCER_APU_TYPE));
+  asm volatile("csrw 0x32E, %0" : : "r"(1<<CSR_PCER_APU_CONT));
+  asm volatile("csrw 0x32F, %0" : : "r"(1<<CSR_PCER_APU_WB));
 #endif
 }