Chi Lo e1755541cc Fix TRT timing cache test (#15588) ... TRT EP test for timing cache has wrong logic where it enables timing cache for both sessions to compare the trt engine build time, that's why CI got some intermittent failures. This PR disabled the timing cache test for comparing the engine build time between enabling/disabling timing cache until we find a model that can benefit from timing cache.		2023-04-25 10:20:26 -07:00
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contrib_ops	Fix cuda 12.1 windows Build (#15614)	2023-04-24 10:02:35 -07:00
core	remove compute optimizer from lte (learning on the edge) builds (#15637)	2023-04-24 15:57:15 -07:00
python	[ROCm] Add stable diffusion benchmark results for MI100 (#15646)	2023-04-23 18:29:35 +08:00
test	Fix TRT timing cache test (#15588)	2023-04-25 10:20:26 -07:00
tool/etw	Run clang-format in CI (#15524)	2023-04-18 09:26:58 -07:00
wasm	[js/web] WebGPU backend via JSEP (#14579)	2023-04-24 15:21:18 -07:00
__init__.py	Adopt linrtunner as the linting tool - take 2 (#15085)	2023-03-24 15:29:03 -07:00
ReformatSource.ps1	Run clang-format in CI (#15524)	2023-04-18 09:26:58 -07:00
ReformatSourcePython.bat
VSCodeCoverage.runsettings