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### Description This pull request introduces the necessary changes to enable RISC-V 64-bit cross-compiling support for the ONNX Runtime on Linux. The RISC-V architecture has gained popularity as an open standard instruction set architecture, and this contribution aims to extend ONNX Runtime's compatibility to include RISC-V, thereby broadening the reach of ONNX models to a wider range of devices. ### Motivation and Context RISC-V is a free and open-source instruction set architecture (ISA) based on established RISC principles. It is provided under open licenses without fees. Due to its extensibility and freedom in both software and hardware, RISC-V is poised for widespread adoption in the future, especially in applications related to AI, parallel computing, and data centers. ### Example Build Command ``` ./build.sh --parallel --config Debug --rv64 --riscv_toolchain_root=/path/to/toolchain/root --skip_tests ``` ### Documentation Updates Relevant sections of the documentation will be updated to reflect the newly supported RISC-V 64-bit cross-compilation feature. https://github.com/microsoft/onnxruntime/pull/19239 --------- Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com> |
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| .. | ||
| github | ||
| __init__.py | ||
| amd_hipify.py | ||
| build.py | ||
| clean_docker_image_cache.py | ||
| compile_triton.py | ||
| coverage.py | ||
| gen_def.py | ||
| get_docker_image.py | ||
| logger.py | ||
| op_registration_utils.py | ||
| op_registration_validator.py | ||
| patch_manylinux.py | ||
| policheck_exclusions.xml | ||
| reduce_op_kernels.py | ||
| replace_urls_in_deps.py | ||
| requirements-transformers-test.txt | ||
| set-trigger-rules.py | ||
| update_tsaoptions.py | ||
| upload_python_package_to_azure_storage.py | ||