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https://github.com/saymrwulf/onnxruntime.git
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fff85a6a35
* Add kernels for AMD GPU. This PR is mostly about GPU kernels for ROCm EP. Due to similar GPU programming language (CUDA and HIP and similar math library calls, one principle in ROCM EP design is to share CUDA kernels as much as possible for ROCm. Thus, the script amd_hipify.py has been created for converting CUDA kernels to ROCm HIP kernels automatically during compilation phase. But, for some reasons such as perf issue, syntax difference..., some converted kernels need some manual intervention. These kernels will be checked in the repo physically for now. In order to avoid manual intervention, the plan is to refactor CUDA kernels to make them portable between CUDA EP and ROCm EP as much as possible. Please refer to "HIP Porting Guide" for details. * like lamb, multi-tensor-apply needs to be disabled for IsAllFiniteOp and ReduceAllL2, current AMD GPU compiler has perf issue for kernel parameter which is a structure with "pass by value". * Use hipMemsetAsync and add checks on HIP calls. * move the generated files to build folder. Co-authored-by: Jesse Benson <jesseb@microsoft.com>
69 lines
3.6 KiB
C++
69 lines
3.6 KiB
C++
// Copyright (c) Microsoft Corporation. All rights reserved.
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// Licensed under the MIT License.
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#include "contrib_ops/cuda/math/binary_elementwise_ops.h"
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#include "contrib_ops/cuda/math/binary_elementwise_ops_impl.h"
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using namespace onnxruntime::common;
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namespace onnxruntime {
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namespace contrib {
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namespace cuda {
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#define CONTRIB_BINARY_ELEMENTWISE_REGISTER_KERNEL_TYPED(x, ver, T) \
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ONNX_OPERATOR_TYPED_KERNEL_EX( \
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x, \
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kMSDomain, \
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ver, \
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T, \
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kCudaExecutionProvider, \
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KernelDefBuilder().TypeConstraint("T", DataTypeImpl::GetTensorType<T>()), \
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x<T>);
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#define CONTRIB_BINARY_ELEMENTWISE_COMPUTE(x, T) \
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template <> \
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Status x<T>::ComputeInternal(OpKernelContext* context) const { \
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BinaryElementwisePreparation prepare; \
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ORT_RETURN_IF_ERROR(Prepare(context, &prepare)); \
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Impl_##x<typename ToCudaType<T>::MappedType>( \
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prepare.output_rank_or_simple_broadcast, \
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&prepare.lhs_padded_strides, \
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reinterpret_cast<const typename ToCudaType<T>::MappedType*>(prepare.lhs_tensor->template Data<T>()), \
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&prepare.rhs_padded_strides, \
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reinterpret_cast<const typename ToCudaType<T>::MappedType*>(prepare.rhs_tensor->template Data<T>()), \
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&prepare.fdm_output_strides, \
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prepare.fdm_H, \
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prepare.fdm_C, \
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reinterpret_cast<typename ToCudaType<T>::MappedType*>(prepare.output_tensor->template MutableData<T>()), \
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prepare.output_tensor->Shape().Size()); \
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return Status::OK(); \
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}
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#define CONTRIB_BINARY_OP_TYPED(name, ver, T) \
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CONTRIB_BINARY_ELEMENTWISE_REGISTER_KERNEL_TYPED(name, ver, T) \
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CONTRIB_BINARY_ELEMENTWISE_COMPUTE(name, T)
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// since different ops has different types, we cannot use BINARY_OPS() directly
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// the postfix of means the types supported by the op:
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// B: uint8_t
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// W: uint16_t
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// U: uint32_t
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// Z: uint64_t
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// C: int8_t
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// S: int16_t
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// I: int32_t
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// L: int64_t
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// H: float16
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// F: float
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// D: double
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// O: bool
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#define CONTRIB_BINARY_OP_HFD(name, ver) \
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CONTRIB_BINARY_OP_TYPED(name, ver, MLFloat16) \
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CONTRIB_BINARY_OP_TYPED(name, ver, float) \
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CONTRIB_BINARY_OP_TYPED(name, ver, double)
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CONTRIB_BINARY_OP_HFD(BiasGelu, 1)
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} // namespace cuda
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} // namespace contrib
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} // namespace onnxruntime
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