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3c49aacd56
Disable __cpuid check on arm64 builds as intrinsic is not available Motivation Breaking the arm64 build. Co-authored-by: Sheil Kumar <sheilk@microsoft.com>
109 lines
3.3 KiB
C++
109 lines
3.3 KiB
C++
// Copyright (c) Microsoft Corporation. All rights reserved.
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// Licensed under the MIT License.
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#include "lib/Api/pch/pch.h"
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#include "HardwareCoreEnumerator.h"
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namespace WINMLP {
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struct LogicalProcessorInformation {
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std::unique_ptr<char[]> Buffer;
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size_t Length;
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};
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struct CoreCounter {
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uint32_t PhysicalCores = 0;
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uint32_t Num2CacheCores = 0;
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};
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static LogicalProcessorInformation GetLogicalProcessorInfos(LOGICAL_PROCESSOR_RELATIONSHIP relationship) {
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DWORD length = 0;
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DWORD rc = GetLogicalProcessorInformationEx(relationship, nullptr, &length);
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assert(rc == FALSE);
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auto processorInformationBytes = std::make_unique<char[]>(length);
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rc = GetLogicalProcessorInformationEx(
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relationship, reinterpret_cast<PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX>(processorInformationBytes.get()), &length
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);
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assert(rc == TRUE);
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return {std::move(processorInformationBytes), length};
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}
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uint32_t CountSetBits(DWORD input) {
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uint32_t c;
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for (c = 0; input; c++) {
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input &= input - 1;
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}
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return c;
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}
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static CoreCounter GetNumberOPhysicalAndEngineeringCores() {
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auto logicalProcessorInformation = GetLogicalProcessorInfos(RelationAll);
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CoreCounter cores;
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DWORD dwLevel2GroupMask = 0;
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DWORD dwLevel3GroupMask = 0;
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size_t read = 0;
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PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX currentProcessorInfo = NULL;
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while ((read + FIELD_OFFSET(SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX, Processor)) < logicalProcessorInformation.Length
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) {
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currentProcessorInfo =
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reinterpret_cast<PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX>(logicalProcessorInformation.Buffer.get() + read);
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if ((read + currentProcessorInfo->Size) > logicalProcessorInformation.Length) {
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break;
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}
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switch (currentProcessorInfo->Relationship) {
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case RelationProcessorCore:
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cores.PhysicalCores++;
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break;
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case RelationCache:
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if (currentProcessorInfo->Cache.Level == 2) {
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dwLevel2GroupMask |= currentProcessorInfo->Cache.GroupMask.Mask;
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} else if (currentProcessorInfo->Cache.Level == 3) {
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dwLevel3GroupMask |= currentProcessorInfo->Cache.GroupMask.Mask;
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}
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break;
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}
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read += currentProcessorInfo->Size;
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}
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cores.Num2CacheCores = CountSetBits(dwLevel2GroupMask & ~dwLevel3GroupMask);
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return cores;
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}
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uint32_t HardwareCoreEnumerator::DefaultIntraOpNumThreads() {
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// # of physical cores = # of P cores + # of E Cores + # of Soc Cores.
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// # of logical cores = # of P cores x 2 (if hyper threading is enabled) + # of E cores + # of Soc Cores.
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auto cores = GetNumberOPhysicalAndEngineeringCores();
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#if !defined(_M_ARM64) && !defined(__aarch64__)
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const int kVendorID_Intel[3] = {0x756e6547, 0x6c65746e, 0x49656e69}; // "GenuntelineI"
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int regs_leaf0[4];
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int regs_leaf7[4];
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__cpuid(regs_leaf0, 0);
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__cpuid(regs_leaf7, 0x7);
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auto isIntel = (kVendorID_Intel[0] == regs_leaf0[1]) && (kVendorID_Intel[1] == regs_leaf0[2]) &&
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(kVendorID_Intel[2] == regs_leaf0[3]);
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auto isHybrid = (regs_leaf7[3] & (1 << 15));
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if (isIntel && isHybrid) {
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// We want to use the number of physical cores, but exclude soc cores
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// On Intel Hybrid processors, numSocCores == cores.Num2CacheCores
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return cores.PhysicalCores - cores.Num2CacheCores;
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}
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#endif
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return cores.PhysicalCores;
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}
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} // namespace WINMLP
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