stevenlix ce0025d3f2 Fallback Pow op in layer norm to FP32 in TRT to avoid overflow (#13639) ... Accuracy loss is observed when transformer models such as BERT, DeBERTa, ViT are running in TRT FP16 mode. The cause is that overflow happens at Pow op in layer norm. This PR provides the option to force Pow to run in TRT FP32 precision if overflow occurs. Co-authored-by: Ubuntu <azureuser@orteplinuxdev.bxgbzpva45kedp3rhbsbit4phb.jx.internal.cloudapp.net>		2022-11-29 13:37:31 -08:00
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acl
armnn
cann	Add CANN EP (#12416)	2022-09-22 14:53:40 -07:00
coreml
cpu
cuda	Allow CUDA EP enable or disable TunableOp via session options and environment variable (#13601)	2022-11-15 14:43:54 +08:00
dml	Enable building with a GDK (#11126)	2022-04-07 15:06:31 -07:00
dnnl
nnapi
openvino	Openvino ep 2022.2 v4.2 (#13023)	2022-09-22 12:31:40 -07:00
rknpu
tensorrt	Fallback Pow op in layer norm to FP32 in TRT to avoid overflow (#13639)	2022-11-29 13:37:31 -08:00
tvm	[TVM EP] code refactor (#10655)	2022-03-16 13:55:04 +01:00
vitisai
winml	Enable creating OrtValues from ID3D12Resources from the onnxruntime C-API (#9686)	2021-11-13 03:34:54 -08:00
providers.h