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https://github.com/saymrwulf/onnxruntime.git
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MLAS: enable SSE 4.1 path for x86 build (#8127)
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3 changed files with 6 additions and 8 deletions
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@ -704,6 +704,8 @@ struct MLAS_PLATFORM {
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#if defined(MLAS_TARGET_AMD64_IX86)
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MLAS_GEMM_FLOAT_KERNEL* GemmFloatKernel;
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const MLAS_GEMM_U8X8_DISPATCH* GemmU8S8Dispatch;
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const MLAS_GEMM_U8X8_DISPATCH* GemmU8U8Dispatch;
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#endif
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#if defined(MLAS_TARGET_AMD64)
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@ -711,10 +713,8 @@ struct MLAS_PLATFORM {
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MLAS_SGEMM_KERNEL_M1_ROUTINE* KernelM1TransposeBRoutine;
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MLAS_SGEMM_TRANSPOSE_PACKB_BLOCK_ROUTINE* TransposePackB16x4Routine;
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MLAS_GEMM_DOUBLE_KERNEL* GemmDoubleKernel;
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const MLAS_GEMM_U8X8_DISPATCH* GemmU8S8Dispatch;
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MLAS_GEMM_U8S8_KERNEL* GemmU8S8Kernel;
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MLAS_GEMV_U8S8_KERNEL* GemvU8S8Kernel;
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const MLAS_GEMM_U8X8_DISPATCH* GemmU8U8Dispatch;
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MLAS_GEMM_U8U8_KERNEL* GemmU8U8Kernel;
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MLAS_CONV_FLOAT_KERNEL* ConvNchwFloatKernel;
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MLAS_CONV_FLOAT_KERNEL* ConvNchwcFloatKernel;
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@ -126,13 +126,13 @@ Return Value:
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//
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this->GemmFloatKernel = MlasGemmFloatKernelSse;
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this->GemmU8S8Dispatch = &MlasGemmU8X8DispatchSse;
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this->GemmU8U8Dispatch = &MlasGemmU8X8DispatchSse;
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#if defined(MLAS_TARGET_AMD64)
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this->TransposePackB16x4Routine = MlasSgemmTransposePackB16x4Sse;
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this->GemmDoubleKernel = MlasGemmDoubleKernelSse;
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this->GemmU8S8Dispatch = &MlasGemmU8X8DispatchSse;
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this->GemmU8U8Dispatch = &MlasGemmU8X8DispatchSse;
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this->ConvNchwFloatKernel = MlasConvNchwFloatKernelSse;
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this->ConvNchwcFloatKernel = MlasConvNchwcFloatKernelSse;
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this->ConvDepthwiseFloatKernel = MlasConvDepthwiseFloatKernelSse;
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@ -170,7 +170,7 @@ Return Value:
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__cpuid(1, Cpuid1[0], Cpuid1[1], Cpuid1[2], Cpuid1[3]);
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#endif
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#if defined(MLAS_TARGET_AMD64) && defined(_MSC_VER)
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#if defined(_MSC_VER)
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//
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// Check if the processor supports SSE 4.1 instructions.
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@ -61,14 +61,12 @@ MlasGemmU8X8GetDispatch(
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MLAS_UNREFERENCED_PARAMETER(BIsSigned);
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#if defined(MLAS_TARGET_AMD64)
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#if defined(MLAS_TARGET_AMD64_IX86)
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if (BIsSigned) {
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GemmU8X8Dispatch = MlasPlatform.GemmU8S8Dispatch;
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} else {
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GemmU8X8Dispatch = MlasPlatform.GemmU8U8Dispatch;
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}
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#elif defined(MLAS_SSE2_INTRINSICS)
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GemmU8X8Dispatch = &MlasGemmU8X8DispatchSse;
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#elif defined(MLAS_NEON64_INTRINSICS)
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GemmU8X8Dispatch = MlasPlatform.GemmU8X8Dispatch;
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#elif defined(MLAS_NEON32_INTRINSICS) && !defined(_MSC_VER)
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