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Resize optimization for all architectures (#11956)
With this patch, it optimizes Resize when the input X is 4D int8/uint8 tensor and the mode is linear by: * Transforming NCHW Resize to NHWC variant * Using the NHWC Resize kernel without floating-point computation It improves DeepLab V3 with uint8 quantization by 19% on X64. It also improves Resize of DeepLab V3 with int8 quantization by 15%~18% on X64.
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3 changed files with 2 additions and 14 deletions
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@ -1765,10 +1765,9 @@ static bool CanNodeSkipCostCheck(const OptimizerCtx& ctx, const api::NodeRef& no
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// Inclusion of MaxPool is a hack because it has higher perf in the NHWC variant when supported.
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return true;
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}
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#if defined(_M_ARM64) || defined(__aarch64__) || defined(_M_ARM) || defined(__arm__)
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if (node.IsOp("Resize")) {
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// Resize is included because it has higher perf in the NHWC variant when
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// the input X is 4D int8 tensor and the mode is linear on ARM
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// the input X is 4D int8 tensor and the mode is linear
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auto X_value_info = ctx.graph.GetValueInfo(node.Inputs()[0]);
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auto X_shape = X_value_info->Shape();
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auto X_dtype = X_value_info->DType();
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@ -1778,9 +1777,6 @@ static bool CanNodeSkipCostCheck(const OptimizerCtx& ctx, const api::NodeRef& no
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return true;
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}
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}
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#else
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(void)ctx;
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#endif
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return false;
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}
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@ -1173,7 +1173,6 @@ Status Upsample<T>::BaseCompute(OpKernelContext* context,
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output_height * output_width > 64 ? context->GetOperatorThreadPool() : nullptr);
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} else {
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if (use_extrapolation_) {
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#if defined(_M_ARM64) || defined(__aarch64__) || defined(_M_ARM) || defined(__arm__)
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if (!is_2D &&
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(Y->GetElementType() == ONNX_NAMESPACE::TensorProto_DataType_UINT8 ||
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Y->GetElementType() == ONNX_NAMESPACE::TensorProto_DataType_INT8)) {
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@ -1183,17 +1182,13 @@ Status Upsample<T>::BaseCompute(OpKernelContext* context,
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alloc, get_original_coordinate_,
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output_height * output_width * num_channels > 64 ? context->GetOperatorThreadPool() : nullptr);
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} else {
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#endif
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NhwcUpsampleBilinear<T, true>(
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batch_size, num_channels, input_height, input_width, output_height, output_width,
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height_scale, width_scale, roi, extrapolation_value_, X->Data<T>(), Y->MutableData<T>(),
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alloc, get_original_coordinate_,
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output_height * output_width * num_channels > 64 ? context->GetOperatorThreadPool() : nullptr);
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#if defined(_M_ARM64) || defined(__aarch64__) || defined(_M_ARM) || defined(__arm__)
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}
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#endif
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} else {
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#if defined(_M_ARM64) || defined(__aarch64__) || defined(_M_ARM) || defined(__arm__)
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if (!is_2D &&
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(Y->GetElementType() == ONNX_NAMESPACE::TensorProto_DataType_UINT8 ||
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Y->GetElementType() == ONNX_NAMESPACE::TensorProto_DataType_INT8)) {
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@ -1203,15 +1198,12 @@ Status Upsample<T>::BaseCompute(OpKernelContext* context,
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alloc, get_original_coordinate_,
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output_height * output_width * num_channels > 64 ? context->GetOperatorThreadPool() : nullptr);
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} else {
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#endif
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NhwcUpsampleBilinear<T, false>(
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batch_size, num_channels, input_height, input_width, output_height, output_width,
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height_scale, width_scale, roi, extrapolation_value_, X->Data<T>(), Y->MutableData<T>(),
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alloc, get_original_coordinate_,
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output_height * output_width * num_channels > 64 ? context->GetOperatorThreadPool() : nullptr);
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#if defined(_M_ARM64) || defined(__aarch64__) || defined(_M_ARM) || defined(__arm__)
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}
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#endif
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}
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}
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return Status::OK();
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@ -255,7 +255,7 @@ void NhwcUpsampleBilinearInteger(const int32_t batch_size,
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const T* const Xdata = XdataBase + n * (input_height * input_width) * num_channels;
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T* const Ydata = YdataBase + n * (output_height * output_width) * num_channels;
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concurrency::ThreadPool::TryParallelFor(
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tp, output_height * output_width,
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tp, static_cast<std::ptrdiff_t>(output_height) * output_width,
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static_cast<double>(num_channels * 2),
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[&](std::ptrdiff_t first, std::ptrdiff_t last) {
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for (std::ptrdiff_t i = first; i < last; ++i) {
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