saymrwulf/litex-boards
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litex-boards/litex_boards
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Josuah Demangeon cbcf6df26f lattice_ecp5_evn: add_jtagbone flag 
This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
2023-07-31 13:53:24 +02:00
..
platforms platforms/ti60_f225: Add connector numbering to ease review/schematic comparison. 2023-07-21 09:08:22 +02:00
prog Basic SoC for Opal Kelly XEM8320 2023-02-28 13:19:12 -07:00
targets lattice_ecp5_evn: add_jtagbone flag 2023-07-31 13:53:24 +02:00
__init__.py litex_boards: Remove short imports since not really longer useful and mess up Python imports. 2022-05-03 17:53:57 +02:00