diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
index d1fb956c..dcf0495d 100755
--- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -141,7 +141,7 @@ class BaseSoC(SoCCore):
 
         # UartBone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone("serial", baudrate=1e6)
+            self.add_uartbone(baudrate=1e6)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py
index e8142b20..b0285de3 100755
--- a/litex_boards/targets/antmicro_lpddr4_test_board.py
+++ b/litex_boards/targets/antmicro_lpddr4_test_board.py
@@ -108,7 +108,7 @@ class BaseSoC(SoCCore):
 
         # UartBone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone("serial", baudrate=1e6)
+            self.add_uartbone(baudrate=1e6)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py
index 5059f929..873ff5e4 100755
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@@ -196,7 +196,7 @@ class BaseSoC(SoCCore):
         if with_uartbone:
             if board != "i5a-907":
                 raise ValueError("uartbone only supported on i5a-907")
-            self.add_uartbone(name="uartbone")
+            self.add_uartbone(uart_name="uartbone")
 
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index 685532dc..9a538876 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -98,7 +98,7 @@ class BaseSoC(SoCCore):
         # Add a UARTBone bridge --------------------------------------------------------------------
         debug_uart = False
         if debug_uart:
-            self.add_uartbone(name="serial")
+            self.add_uartbone()
 
 # Flash --------------------------------------------------------------------------------------------
 
diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py
index 3c8158c3..938f10ca 100755
--- a/litex_boards/targets/mnt_rkx7.py
+++ b/litex_boards/targets/mnt_rkx7.py
@@ -183,7 +183,7 @@ class BaseSoC(SoCCore):
         # LiteScope Analyzer -----------------------------------------------------------------------
         if with_analyzer:
             from litescope import LiteScopeAnalyzer
-            self.add_uartbone(name="debug_serial")
+            self.add_uartbone(uart_name="debug_serial")
             analyzer_signals = [
                 ulpi_data.din,
                 utmi.linestate,
diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py
index 6dc261f5..07d59f46 100755
--- a/litex_boards/targets/terasic_deca.py
+++ b/litex_boards/targets/terasic_deca.py
@@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
 
         # UARTbone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"])
+            self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
 
         # JTAGbone ---------------------------------------------------------------------------------
         if with_jtagbone: