diff --git a/litex_boards/platforms/enclustra_mercury_kx2.py b/litex_boards/platforms/enclustra_mercury_kx2.py index f631183d..b986f4fa 100644 --- a/litex_boards/platforms/enclustra_mercury_kx2.py +++ b/litex_boards/platforms/enclustra_mercury_kx2.py @@ -2,6 +2,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2020 Mark Standke +# Copyright (c) 2023 Hans Baier # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * @@ -81,6 +82,193 @@ _io = [ ("ddram_vsel", 0, Pins('AA3'), IOStandard("SSTL15"), Misc("SLEW=SLOW")), ] +_connectors = [ + ("A", { + 15 : "W20", 16 : "AA23", + 17 : "Y21", 18 : "AB24", + 19 : "AD21", + 21 : "AE21", 22 : "AB21", + 24 : "AC21", + 25 : "AE22", + 27 : "AF22", 28 : "AB22", + 30 : "AC22", + 31 : "V21", + 33 : "W21", 34 : "AE23", + 36 : "AF23", + 37 : "V23", + 39 : "V24", 40 : "AF24", + 42 : "AF25", + 43 : "U24", + 45 : "U25", 46 : "Y22", + 48 : "AA22", + 49 : "AC23", + 51 : "AC24", 52 : "AD25", + 54 : "AE25", + 55 : "W25", + 57 : "W26", 58 : "AD23", + 60 : "AD24", + 61 : "U26", + 63 : "V26", 64 : "U22", + 66 : "V22", + 67 : "AB26", + 69 : "AC26", 70 : "W23", + 72 : "W24", + 73 : "AA25", + 75 : "AB25", 76 : "AD26", + 78 : "AE26", + 79 : "U21", + 81 : "Y20", 82 : "Y25", + 84 : "Y26", + 85 : "Y23", + 87 : "AA24", 88 : "D23", + 90 : "D24", + 91 : "C21", 92 : "E21", + 93 : "B21", 94 : "E22", + 95 : "D26", + 97 : "C26", 98 : "D21", + 100 : "C22", + 101 : "A23", + 103 : "A24", 104 : "F22", + 105 : "B20", 106 : "E23", + 107 : "A20", + }), + ("B", { + 1 : "D6" , + 3 : "D5" , 4: "H6", + 5 : "F6" , 6: "H5", + 7 : "F5" , + 10: "K6", + 12: "K5", + 13 : "P2" , + 16: "R4", + 17 : "P1" , + 20: "R3", + 21 : "M2" , + 24: "N4", + 25 : "M1" , + 28: "N3", + 29 : "K2" , + 32: "L4", + 33 : "K1" , + 36: "L3", + 37 : "H2" , + 40: "J4", + 41 : "H1" , + 44: "J3", + 45 : "F2" , + 47 : "F1" , 48: "G4", + 50: "G3", + 51 : "D2" , + 53 : "D1" , 54: "E4", + 56: "E3", + 57 : "G11", + 59 : "F10", 60: "C4", + 62: "C3", + 63 : "B2" , + 65 : "B1" , 66: "B6", + 68: "B5", + 69 : "A4" , + 71 : "A3" , 72: "F19", + 74: "E20", + 75 : "C14", + 77 : "C13", 78: "H17", + 80: "H18", + 81 : "D14", + 83 : "D13", 84: "G19", + 86: "F20", + 87 : "J13", + 89 : "H13", 90: "L19", + 91 : "F14", 92: "L20", + 93 : "F13", 94: "K20", + 96: "J20", + 97 : "E13", + 99 : "E12", 100: "M17", + 101 : "G12", 102: "L18", + 103 : "F12", 104: "L17", + 106: "K18", + 107 : "J11", + 109 : "J10", 110: "K16", + 111 : "H12", 112: "K17", + 113 : "H11", 114: "J18", + 116: "J19", + 117 : "G10", + 119 : "G9" , 120: "H19", + 122: "G20", + 123 : "E11", 124: "D19", + 125 : "D11", 126: "D20", + + 129 : "A13", 130: "G17", + 131 : "A12", 132: "F18", + 133 : "B10", + 135 : "A10", 136: "C17", + 138: "C18", + 139 : "B12", + 141 : "B11", 142: "C16", + 144: "B16", + 145 : "H14", + 147 : "G14", 148: "B17", + 150: "A17", + 151 : "C12", + 153 : "C11", 154: "E18", + 156: "D18", + 157 : "B14", + 159 : "A14", 160: "C19", + 162: "B19", + 163 : "B15", 164: "A18", + 165 : "A15", 166: "A19", + }), + ("C", { + 69: "J8", + 71: "J14", 72 : "K15", + 74 : "M16", + 75: "A9", + 77: "A8", 78 : "G15", + 79: "C9", 80 : "F15", + 81: "B9", 82 : "J15", + 84 : "J16", + 85: "D9", + 87: "D8", 88 : "F17", + 89: "E10", 90 : "E17", + 91: "D10", 92 : "E15", + 94 : "E16", + 95: "F9", + 97: "F8", 98 : "H16", + 99: "H9", 100 : "G16", + 101: "H8", 102 : "D15", + 104 : "D16", + 105: "N18", + 107: "M19", 108 : "P16", + 109: "R16", 110 : "N17", + 111: "R17", 113 : "U17", + 114 : "T17", + 115: "P23", + 117: "N23", 118 : "R18", + 119: "T24", 120 : "P18", + 121: "T25", 122 : "R22", + 124 : "R23", + 125: "N19", + 127: "M20", 128 : "P24", + 129: "T18", 130 : "N24", + 131: "T19", 132 : "P19", + 134 : "P20", + 135: "U19", + 137: "U20", 138 : "T22", + 139: "T20", 140 : "T23", + 141: "R20", 142 : "K25", + 144 : "K26", + 145: "R25", + 147: "P25", 148 : "N21", + 150 : "N22", + 151: "R21", + 153: "P21", 154 : "M24", + 156 : "L24", + 157: "M21", 160 : "M25", + 159: "M22", 162 : "L25", + 161: "R26", 164 : "N26", + 163: "P26", 166 : "M26", + }) +] + # Platform ----------------------------------------------------------------------------------------- class Platform(Xilinx7SeriesPlatform): @@ -88,7 +276,7 @@ class Platform(Xilinx7SeriesPlatform): default_clk_period = 1e9/200e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xc7k160tffg676-2", _io, toolchain=toolchain) + Xilinx7SeriesPlatform.__init__(self, "xc7k160tffg676-2", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]") self.add_platform_command("set_property CFGBVS GND [current_design]") # DDR3 is connected to banks 32, 33 and 34 @@ -108,6 +296,10 @@ class Platform(Xilinx7SeriesPlatform): # This causes DDR3 to use 1.5V by default self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]") + def add_baseboard(self, bb): + self.add_connector(bb.connectors) + self.add_extension(bb.io) + def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit") diff --git a/litex_boards/platforms/enclustra_st1.py b/litex_boards/platforms/enclustra_st1.py new file mode 100644 index 00000000..b3ad357e --- /dev/null +++ b/litex_boards/platforms/enclustra_st1.py @@ -0,0 +1,298 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2023 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc + +class EnclustraST1: + """ + the ST1 baseboard contains standard peripherals + and can be used with a number of different FPGA core boards + the default VCCIO values are from the jumper positions from the example + design in the manual + """ + def __init__(self, vccio_a="1.8V", vccio_b="1.8V", vccio_c="1.8V") -> None: + def strip_v(s, is_a = False): + assert s in [ + "1.2V" if not is_a else None, + "1.8V", # VCC_OUT_B + "2.5V", # VCC_OUT_A + "3.3V" ] + return s.replace(".", "").replace("V", "") + + vccio_a = strip_v(vccio_a) # Bank 12, 14 + vccio_b = strip_v(vccio_b) # Bank 15, 16 + vccio_c = strip_v(vccio_c) # Bank 13 + + self.io = [ + ("clk_ref", 0, + Subsignal("p", Pins("C:7"), IOStandard("LVDS")), + Subsignal("n", Pins("C:9"), IOStandard("LVDS")) + ), + ("clk_ref0", 0, + Subsignal("p", Pins("B:3"), IOStandard("LVDS")), + Subsignal("n", Pins("B:5"), IOStandard("LVDS")) + ), + ("clk_ref1", 0, + Subsignal("p", Pins("C:10"), IOStandard("LVDS")), + Subsignal("n", Pins("C:12"), IOStandard("LVDS")) + ), + ("clk_ref2", 0, + Subsignal("p", Pins("C:3"), IOStandard("LVDS")), + Subsignal("n", Pins("C:5"), IOStandard("LVDS")) + ), + # daughterboard LEDs + ("user_led", 4, Pins("C:142"), IOStandard("LVCMOS" + vccio_c), Misc("SLEW=SLOW")), + ("user_led", 5, Pins("C:144"), IOStandard("LVCMOS" + vccio_c), Misc("SLEW=SLOW")), + ("i2c", 0, + Subsignal("scl", Pins("A:111"), Misc("SLEW=SLOW")), + Subsignal("sda", Pins("A:113"), Misc("SLEW=SLOW")), + Subsignal("int_n", Pins("A:115"), Misc("SLEW=SLOW")), + IOStandard("LVCMOS" + vccio_a) + ), + ("i2c_fpga", 0, + Subsignal("scl", Pins("A:55"), Misc("SLEW=SLOW")), + Subsignal("sda", Pins("A:57"), Misc("SLEW=SLOW")), + IOStandard("LVCMOS" + vccio_a) + ), + ("i2c_mipi_sel", 0, Pins("A:63"), IOStandard("LVCMOS" + vccio_a)), + + # HDMI Bus + ("hdmi", 0, + Subsignal("clk_p", Pins("C:139")), + Subsignal("clk_n", Pins("C:141")), + Subsignal("data0_p", Pins("C:45")), + Subsignal("data0_n", Pins("C:47")), + Subsignal("data1_p", Pins("C:51")), + Subsignal("data1_n", Pins("C:53")), + Subsignal("data2_p", Pins("C:57")), + Subsignal("data2_n", Pins("C:59")), + Subsignal("hpd", Pins("A:61")), + IOStandard("TMDS_33") + ), + ("sfp_tx", 0, # SFP A + Subsignal("p", Pins("C:63")), + Subsignal("n", Pins("C:65")) + ), + ("sfp_rx", 0, # SFP A + Subsignal("p", Pins("C:66")), + Subsignal("n", Pins("C:68")) + ), + ("usb3", 0, + Subsignal("tx_p", Pins("B:29")), + Subsignal("tx_n", Pins("B:33")), + Subsignal("rx_p", Pins("B:32")), + Subsignal("rx_n", Pins("B:36")), + ), + ("usb3", 1, + Subsignal("tx_p", Pins("B:37")), + Subsignal("tx_n", Pins("B:41")), + Subsignal("rx_p", Pins("B:40")), + Subsignal("rx_n", Pins("B:44")), + ), + ("displayport", 0, + Subsignal("aux_in", Pins("A:88")), + Subsignal("aux_out", Pins("A:90")), + Subsignal("aux_oe", Pins("A:92")), + Subsignal("hpd", Pins("A:94")), + Subsignal("lanes_p", Pins("B:21 B:13 B:16 B:24")), + Subsignal("lanes_n", Pins("B:25 B:17 B:20 B:28")), + ), + ("mipi", 0, + Subsignal("clkp", Pins("C:151")), + Subsignal("clkn", Pins("C:153")), + Subsignal("clk_d0lp_p", Pins("C:160")), + Subsignal("clk_d0lp_n", Pins("C:162")), + Subsignal("dp", Pins("C:145 C:154")), + Subsignal("dn", Pins("C:147 C:156")), + IOStandard("MIPI_DPHY") + ), + ("mipi", 1, + Subsignal("clkp", Pins("C:148")), + Subsignal("clkn", Pins("C:150")), + Subsignal("clk_d0lp_p", Pins("C:161")), + Subsignal("clk_d0lp_n", Pins("C:163")), + Subsignal("dp", Pins("C:164 C:157")), + Subsignal("dn", Pins("C:166 C:159")), + IOStandard("MIPI_DPHY") + ), + ] + + connectors = [ + ("FMC", { + "DP0_C2M_P": "B:45", + "DP0_C2M_N": "B:47", + "DP1_C2M_P": "B:51", + "DP1_C2M_N": "B:53", + "CLK1_M2C_P": "B:57", + "CLK1_M2C_N": "B:59", + "DP2_C2M_P": "B:63", + "DP2_C2M_N": "B:65", + "DP3_C2M_P": "B:69", + "DP3_C2M_N": "B:71", + "LA33_P": "B:75", + "LA33_N": "B:77", + "LA32_P": "B:81", + "LA32_N": "B:83", + "LA31_P": "B:87", + "LA31_N": "B:89", + "LA30_P": "B:91", + "LA30_N": "B:93", + "LA29_P": "B:97", + "LA29_N": "B:99", + "LA28_P": "B:101", + "LA28_N": "B:103", + "LA27_P": "B:107", + "LA27_N": "B:109", + "LA26_P": "B:111", + "LA26_N": "B:113", + "LA25_P": "B:117", + "LA25_N": "B:119", + "LA18_CC_P": "B:123", + "LA18_CC_N": "B:125", + "LA24_P": "B:129", + "LA24_N": "B:131", + "LA23_P": "B:133", + "LA23_N": "B:135", + "LA22_P": "B:139", + "LA22_N": "B:141", + "LA21_P": "B:145", + "LA21_N": "B:147", + "LA17_CC_P": "B:151", + "LA17_CC_N": "B:153", + "LA20_P": "B:157", + "LA20_N": "B:159", + "LA19_P": "B:163", + "LA19_N": "B:165", + "DP0_M2C_P": "B:48", + "DP0_M2C_N": "B:50", + "DP1_M2C_P": "B:54", + "DP1_M2C_N": "B:56", + "DP2_M2C_P": "B:60", + "DP2_M2C_N": "B:62", + "DP3_M2C_P": "B:66", + "DP3_M2C_N": "B:68", + "LA16_P": "B:72", + "LA16_N": "B:74", + "CLK0_M2C_P": "B:78", + "CLK0_M2C_N": "B:80", + "LA15_P": "B:84", + "LA15_N": "B:86", + "LA14_P": "B:90", + "LA14_N": "B:92", + "LA13_P": "B:94", + "LA13_N": "B:96", + "LA12_P": "B:100", + "LA12_N": "B:102", + "LA11_P": "B:104", + "LA11_N": "B:106", + "LA10_P": "B:110", + "LA10_N": "B:112", + "LA09_P": "B:114", + "LA09_N": "B:116", + "LA08_P": "B:120", + "LA08_N": "B:122", + "LA07_P": "B:124", + "LA07_N": "B:126", + "LA01_CC_P": "B:130", + "LA01_CC_N": "B:132", + "LA06_P": "B:136", + "LA06_N": "B:138", + "LA05_P": "B:142", + "LA05_N": "B:144", + "LA04_P": "B:148", + "LA04_N": "B:150", + "LA00_CC_P": "B:154", + "LA00_CC_N": "B:156", + "LA03_P": "B:160", + "LA03_N": "B:162", + "LA02_P": "B:164", + "LA02_N": "B:166", + + "DP4_C2M_P": "C:13", + "DP4_C2M_N": "C:17", + "DP5_C2M_P": "C:21", + "DP5_C2M_N": "C:25", + "DP6_C2M_P": "C:29", + "DP6_C2M_N": "C:33", + "DP7_C2M_P": "C:37", + "DP7_C2M_N": "C:41", + "HA13_P": "C:69", + "HA13_N": "C:71", + "HA11_P": "C:75", + "HA11_N": "C:77", + "HA09_P": "C:79", + "HA09_N": "C:81", + "HA07_P": "C:85", + "HA07_N": "C:87", + "HA01_CC_P": "C:89", + "HA01_CC_N": "C:91", + "HA04_P": "C:95", + "HA04_N": "C:97", + "HA02_P": "C:99", + "HA02_N": "C:101", + "HA17_P": "C:135", + "HA17_N": "C:137", + + "GCLK1_M2C_P": "C:4", + "GCLK1_M2C_N": "C:6", + "DP4_M2C_P": "C:16", + "DP4_M2C_N": "C:20", + "DP5_M2C_P": "C:24", + "DP5_M2C_N": "C:28", + "DP6_M2C_P": "C:32", + "DP6_M2C_N": "C:36", + "DP7_M2C_P": "C:40", + "DP7_M2C_N": "C:44", + "HA16_P": "C:48", + "HA16_N": "C:50", + "HA15_P": "C:54", + "HA15_N": "C:56", + "HA14_P": "C:60", + "HA14_N": "C:62", + "HA12_P": "C:72", + "HA12_N": "C:74", + "HA10_P": "C:78", + "HA10_N": "C:80", + "HA08_P": "C:82", + "HA08_N": "C:84", + "HA00_CC_P": "C:88", + "HA00_CC_N": "C:90", + "HA06_P": "C:92", + "HA06_N": "C:94", + "HA05_P": "C:98", + "HA05_N": "C:100", + "HA03_P": "C:102", + "HA03_N": "C:104", + }), + + ("IO1", { + "CLK_P": "C:122", + "CLK_N": "C:124", + "D0_P": "C:115", + "D1_N": "C:117", + "D2_P": "C:129", + "D3_N": "C:131", + "D4_P": "C:125", + "D5_N": "C:127", + "D6_P": "C:119", + "D7_N": "C:121", + "D8_P": "C:109", + "D9_N": "C:111", + "D10_P": "C:105", + "D11_N": "C:107", + "D12_P": "C:138", + "D13_N": "C:140", + "D14_P": "C:132", + "D15_N": "C:134", + "D16_P": "C:128", + "D17_N": "C:130", + "D18_P": "C:118", + "D19_N": "C:120", + "D20_P": "C:112", + "D21_N": "C:114", + "D22_P": "C:108", + "D23_N": "C:110", + }),] diff --git a/litex_boards/targets/enclustra_mercury_kx2.py b/litex_boards/targets/enclustra_mercury_kx2.py index 5466bc2e..7e55790f 100755 --- a/litex_boards/targets/enclustra_mercury_kx2.py +++ b/litex_boards/targets/enclustra_mercury_kx2.py @@ -4,13 +4,14 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2020 Mark Standke +# Copyright (c) 2023 Hans Baier # SPDX-License-Identifier: BSD-2-Clause from migen import * from litex.gen import * -from litex_boards.platforms import enclustra_mercury_kx2 +from litex_boards.platforms import enclustra_mercury_kx2, enclustra_st1 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -31,7 +32,7 @@ class _CRG(LiteXModule): # # # - self.pll = pll = S7MMCM(speedgrade=-2) + self.pll = pll = S7PLL(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst) pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) @@ -45,8 +46,11 @@ class _CRG(LiteXModule): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, **kwargs): + def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, with_st1_baseboard=False, **kwargs): platform = enclustra_mercury_kx2.Platform() + if with_st1_baseboard: + baseboard = enclustra_st1.EnclustraST1() + platform.add_baseboard(baseboard) # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) @@ -78,10 +82,12 @@ def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=enclustra_mercury_kx2.Platform, description="LiteX SoC on KX2.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") + parser.add_argument("--with-st1-baseboard", action="store_true", help="add enclustra ST1 baseboard") args = parser.parse_args() soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, + with_st1_baseboard = args.with_st1_baseboard, **parser.soc_argdict ) builder = Builder(soc, **parser.builder_argdict)