mirror of
https://github.com/saymrwulf/litex-boards.git
synced 2026-07-30 20:07:53 +00:00
targets/machdyne: Switch to LiteXModule for consistency with other targets.
This commit is contained in:
Florent Kermarrec
parent
bd7c4f8424
commit
2eb7419678
3 changed files with 67 additions and 58 deletions
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@ -13,6 +13,9 @@ import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_konfekt
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -36,13 +39,13 @@ from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_video = ClockDomain()
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self.clock_domains.cd_video5x = ClockDomain()
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_video = ClockDomain()
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self.cd_video5x = ClockDomain()
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# Clk / Rst
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clk48 = platform.request("clk48")
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@ -55,25 +58,25 @@ class _CRG(Module):
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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elif sdram_rate == "1:4":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_ps = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.cd_sys_ps = ClockDomain()
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if sdram_rate == "1:2":
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@ -85,14 +88,14 @@ class _CRG(Module):
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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pll2 = ECP5PLL()
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self.submodules.pll2 = pll2
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self.pll2 = pll2
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pll2.register_clkin(clk48, 48e6)
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pll2.create_clkout(self.cd_video, 25e6)
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pll2.create_clkout(self.cd_video5x, 125e6)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll2.create_clkout(self.cd_usb, 48e6)
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pll2.create_clkout(self.cd_usb_12, 12e6)
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@ -109,7 +112,7 @@ class BaseSoC(SoCCore):
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platform = machdyne_konfekt.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Konfekt", **kwargs)
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@ -124,7 +127,7 @@ class BaseSoC(SoCCore):
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else:
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sdrphy_cls = GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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if sdram_device == "W9825G6KH6":
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self.add_sdram("sdram",
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@ -142,20 +145,20 @@ class BaseSoC(SoCCore):
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# DDMI Framebuffer -------------------------------------------------------------------------------------
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self.submodules.videophy = VideoHDMIPHY(platform.request("ddmi"),
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self.videophy = VideoHDMIPHY(platform.request("ddmi"),
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clock_domain="video")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
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clock_domain="video", format="rgb565")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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@ -14,6 +14,9 @@ import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_kopflos
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -38,14 +41,14 @@ from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain()
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self.clock_domains.cd_init = ClockDomain()
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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self.cd_init = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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@ -62,7 +65,7 @@ class _CRG(Module):
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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@ -86,12 +89,12 @@ class _CRG(Module):
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]
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pll2 = ECP5PLL()
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self.submodules.pll2 = pll2
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self.pll2 = pll2
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pll2.register_clkin(clk48, 48e6)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll2.create_clkout(self.cd_usb, 48e6)
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pll2.create_clkout(self.cd_usb_12, 12e6)
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@ -108,7 +111,7 @@ class BaseSoC(SoCCore):
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platform = machdyne_kopflos.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs)
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@ -125,7 +128,7 @@ class BaseSoC(SoCCore):
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sdram_module = available_sdram_modules.get(sdram_device)
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ddram_pads = platform.request("ddram")
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self.submodules.ddrphy = ECP5DDRPHY(
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self.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq,
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
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@ -140,14 +143,14 @@ class BaseSoC(SoCCore):
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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if with_ethernet:
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.submodules.ethphy = LiteEthPHYRMII(
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self.ethphy = LiteEthPHYRMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"),
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with_hw_init_reset=True,
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@ -156,7 +159,7 @@ class BaseSoC(SoCCore):
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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@ -14,6 +14,9 @@ import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_noir
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -37,16 +40,16 @@ from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_video = ClockDomain()
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self.clock_domains.cd_video5x = ClockDomain()
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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self.cd_init = ClockDomain()
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self.cd_video = ClockDomain()
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self.cd_video5x = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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@ -63,7 +66,7 @@ class _CRG(Module):
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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@ -87,14 +90,14 @@ class _CRG(Module):
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]
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pll2 = ECP5PLL()
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self.submodules.pll2 = pll2
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self.pll2 = pll2
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pll2.register_clkin(clk48, 48e6)
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pll2.create_clkout(self.cd_video, 25e6)
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pll2.create_clkout(self.cd_video5x, 125e6)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll2.create_clkout(self.cd_usb, 48e6)
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pll2.create_clkout(self.cd_usb_12, 12e6)
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@ -111,7 +114,7 @@ class BaseSoC(SoCCore):
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platform = machdyne_noir.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs)
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@ -128,7 +131,7 @@ class BaseSoC(SoCCore):
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sdram_module = available_sdram_modules.get(sdram_device)
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ddram_pads = platform.request("ddram")
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self.submodules.ddrphy = ECP5DDRPHY(
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self.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq,
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
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@ -143,20 +146,20 @@ class BaseSoC(SoCCore):
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# DDMI Framebuffer -------------------------------------------------------------------------------------
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self.submodules.videophy = VideoHDMIPHY(platform.request("ddmi"),
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self.videophy = VideoHDMIPHY(platform.request("ddmi"),
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clock_domain="video")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
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clock_domain="video", format="rgb565")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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