diff --git a/litex_boards/platforms/alinx_axau15.py b/litex_boards/platforms/alinx_axau15.py
index 8c25d1cc..bf9de4f5 100644
--- a/litex_boards/platforms/alinx_axau15.py
+++ b/litex_boards/platforms/alinx_axau15.py
@@ -150,22 +150,40 @@ _connectors = [
         "CLK0_P"        : "T25",
         "CLK1_N"        : "AC21",
         "CLK1_P"        : "AB21",
+        "DP0_M2C_P"     : "Y2",
+        "DP0_M2C_N"     : "Y1",
         "DP1_M2C_P"     : "V2",
         "DP1_M2C_N"     : "V1",
         "DP2_M2C_P"     : "T2",
         "DP2_M2C_N"     : "T1",
         "DP3_M2C_P"     : "P2",
         "DP3_M2C_N"     : "P1",
+        "DP4_M2C_P"     : "M2",
+        "DP4_M2C_N"     : "M1",
+        "DP5_M2C_P"     : "K2",
+        "DP5_M2C_N"     : "K1",
+        "DP6_M2C_P"     : "H2",
+        "DP6_M2C_N"     : "H1",
+        "DP7_M2C_P"     : "F2",
+        "DP7_M2C_N"     : "F1",
+
+        "DP0_C2M_P"     : "AA5",
+        "DP0_C2M_N"     : "AA4",
         "DP1_C2M_P"     : "W5",
         "DP1_C2M_N"     : "W4",
         "DP2_C2M_P"     : "U5",
         "DP2_C2M_N"     : "U4",
         "DP3_C2M_P"     : "R5",
         "DP3_C2M_N"     : "R4",
-        "DP0_C2M_P"     : "AA5",
-        "DP0_C2M_N"     : "AA4",
-        "DP0_M2C_P"     : "Y2",
-        "DP0_M2C_N"     : "Y1",
+        "DP4_C2M_P"     : "N5",
+        "DP4_C2M_N"     : "N4",
+        "DP5_C2M_P"     : "L5",
+        "DP5_C2M_N"     : "L4",
+        "DP6_C2M_P"     : "J5",
+        "DP6_C2M_N"     : "J4",
+        "DP7_C2M_P"     : "G5",
+        "DP7_C2M_N"     : "G4",
+        
         "LA06_P"        : "N23",
         "LA06_N"        : "P23",
         "LA10_P"        : "W25",
diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py
index fbd8986b..327141c6 100755
--- a/litex_boards/targets/alinx_axau15.py
+++ b/litex_boards/targets/alinx_axau15.py
@@ -56,7 +56,7 @@ class BaseSoC(SoCCore):
         with_etherbone  = False,
         eth_ip          = "192.168.1.50",
         with_led_chaser = True,
-        with_pcie       = True,
+        with_pcie       = False,
         **kwargs):
         platform = alinx_axau15.Platform()
 
@@ -145,7 +145,6 @@ def main():
     if args.load:
         prog = soc.platform.create_programmer()
         prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
-        # TODO: add option for FrontPanel Programming
 
 if __name__ == "__main__":
     main()